Storage Contact Area Expansion via Sacrificial Layer Removal

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Solution Overview

Problem

The increasing integration density of semiconductor devices poses challenges in effectively increasing the area of storage contacts while minimizing etching damage and maintaining a recess-free structure to reduce the distance between the storage contact and the gate electrode.

Innovation Solution

The method involves forming a sacrificial layer under bit line sidewall spacers that overlap active regions, which are then removed to increase the contact area of storage plugs, thereby reducing storage contact resistance and maintaining a recess-free structure of the active region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional methods are used to increase storage contact area, then the contact area increases, but etching damage to the storage substrate increases

Engineering Contradiction:
Improvestorage contact areaVSAvoidetching damage
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

A sacrificial layer is introduced as an intermediary element between the storage contact and the active region. This sacrificial layer enables the formation of larger storage contact openings without directly etching into the active region, thereby increasing storage contact area while minimizing etching damage to the substrate.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial layer is formed in advance before the storage contact openings are created. By preparing this removable layer beforehand, the method allows for subsequent formation of enlarged storage contacts without requiring deep etching into the active region, thus reducing etching damage while achieving increased contact area.

Inventive Principle:
Principle #10Preliminary action

2Area of stationary object

If the storage contact area is increased by conventional means, then the contact resistance decreases, but the active region develops a recess structure that reduces distance to the gate electrode

Engineering Contradiction:
Improvestorage contact areaVSAvoidrecess-free structure
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The sacrificial layer serves as a mediator that fills the space between the storage contact opening and the active region. When the sacrificial layer is removed, it leaves a planar surface rather than a recess, maintaining the distance between the storage contact and gate electrode while still allowing for increased contact area through the enlarged opening.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If etching is performed to create storage contact holes, then the storage contact area increases, but the likelihood of GIDL current increases due to recess formation

Engineering Contradiction:
Improvestorage contact areaVSAvoidGIDL current
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The sacrificial layer acts as a protective intermediary during the storage contact formation process. By removing this sacrificial layer instead of etching directly into the active region, the method achieves increased storage contact area without creating the recess structures that would otherwise lead to higher GIDL current.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8835252B2Methods of fabricating semiconductor devices having increased areas of storage contacts
Publication Date: 2014.09.16 SAMSUNG ELECTRONICS CO LTD
  • US8835252B2 patent drawing
  • US8835252B2 patent drawing
  • US8835252B2 patent drawing

AI summary

Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.