Storage Control Apparatus Address Jump Detection
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Solution Overview
Problem
Conventional solutions for handling continuous write access requests in processors inefficiently switch between write allocate and no-write allocate policies due to physical address jumps, leading to reduced performance and efficiency, especially in memory copy operations where data is not repeatedly accessed.
Innovation Solution
A storage control apparatus and method that dynamically select between write allocate and no-write allocate policies based on the number of continuous physical address jumps, using a no-write allocate policy when jumps are less than a preset quantity and switching to write allocate only when jumps exceed this threshold, thereby optimizing write access requests and improving processor efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the no-write allocate policy is used for continuous write access requests with physical address jumps, then processor efficiency is improved, but data that may be repeatedly accessed is not stored in cache
Solution Approach 1:
The patent applies dynamics by making the write policy adaptive rather than static. The storage control apparatus dynamically switches between no-write allocate and write allocate policies based on detected address jump patterns. When address jumps are detected, the system transitions from no-write allocate to write allocate policy, allowing the system to adapt its behavior to the actual access patterns rather than being constrained by a fixed policy.
Solution Approach 2:
The patent changes the parameter of write policy selection based on address jump detection. Instead of using a fixed write policy, the system monitors physical address patterns and changes the write allocate parameter dynamically. When continuous address jumps are detected beyond a threshold, the system changes from no-write allocate mode to write allocate mode, optimizing performance for the detected access pattern.
2Reliability
If the write allocate policy is used for all write access requests, then data may be stored in cache for repeated access, but processor efficiency is reduced due to unnecessary cache operations
Solution Approach 1:
The system dynamically adjusts the write policy based on real-time address pattern detection. Rather than always using write allocate policy, the apparatus transitions to no-write allocate policy when address continuity is detected, eliminating unnecessary cache operations while maintaining data access reliability when needed.
Solution Approach 2:
The write policy parameter is changed based on detected address patterns. The system monitors whether write access requests follow continuous addresses and changes the write allocate parameter accordingly - using no-write allocate for continuous addresses and write allocate for jumped addresses, optimizing both efficiency and reliability.
3Adaptability or versatility
If the processor switches between write allocate and no-write allocate policies based on address jumps, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the write policy control into distinct detection and execution components. The address detection unit separately identifies address jump patterns, while the logic control unit independently manages policy selection based on detected patterns. This segmentation allows the system to achieve adaptability through clear functional separation rather than complex intertwined logic.
Solution Approach 2:
The patent introduces an intermediary mechanism - the address detection unit - that mediates between the write access requests and the policy selection logic. This intermediary analyzes address patterns and provides information to the logic control unit, simplifying the overall control structure by separating detection from decision-making functions.
4Productivity
If the no-write allocate policy is used for memory copy operations, then processor performance is improved, but data blocks are not temporarily stored in cache
Solution Approach 1:
The system dynamically determines whether to use no-write allocate or write allocate policy based on the specific operation type and address patterns. For memory copy operations with continuous addresses, no-write allocate is used for performance. When address jumps are detected that suggest potential repeated access, the system transitions to write allocate to store data in cache, balancing performance and access time needs.
Solution Approach 2:
The write policy parameter is changed based on operation characteristics and address patterns. The system monitors whether write operations are part of memory copy sequences or involve jumped addresses indicating potential repeated access, and changes the write allocate parameter accordingly to optimize the balance between processor performance and cache access time.
Data Source
AI summary
A storage control apparatus, a storage control method, a processing apparatus, and a computer system are disclosed. The storage control apparatus includes: an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access requests are mapped occurs; and a logic control unit, adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity, the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1. When the quantity of continuous jumps of the physical addresses to which the sequentially arriving write access requests are mapped is less than the preset quantity, embodiments of the present disclosure can keep using the no-write allocate policy, and avoid selecting a write allocate policy during processing of information of a low access probability. Therefore, robustness and stability of the computer system are enhanced.