Storage Control Circuit Address Error Detection Parity
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Solution Overview
Problem
Existing memory error detection systems fail to effectively detect address abnormalities, as they primarily focus on data errors and do not adequately address errors related to abnormal access addresses.
Innovation Solution
A storage control circuit and method that includes an address error detection information generating unit, a control part for storing this information in memory during write access, and an error detecting part for comparing it during read access, using address parity and error correction codes to identify address errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error detection methods (parity, ECC) are used for data strings, then data errors can be detected, but address errors cannot be detected
Solution Approach 1:
The error detection function is segmented into two independent parts: data error detection (using parity/ECC) and address error detection (using address parity). By separating these functions, the system can detect both data errors and address errors without interference, resolving the limitation where only data errors were detectable.
Solution Approach 2:
An address parity bit is introduced as an intermediary element that carries address error detection information. This intermediary allows the system to detect address errors by comparing the stored address parity with the recalculated address parity, enabling detection coverage beyond just data errors.
2Reliability
If address error detection information is stored in memory, then address errors can be detected, but memory capacity is reduced
Solution Approach 1:
The address parity bit is merged with the data storage location, where each memory cell stores both data and its corresponding address parity information. This combining approach allows address error detection without requiring separate dedicated storage space, thus minimizing the impact on memory capacity.
Solution Approach 2:
Instead of storing complete address information for error detection, only the essential parity bits are stored. This partial action approach provides sufficient address error detection capability while consuming minimal memory capacity, balancing reliability improvement with capacity preservation.
3Measurement precision
If address parity and double parity are calculated and stored, then address errors can be detected with higher precision, but processing time increases
Solution Approach 1:
Address parity information is calculated and stored in advance during the write operation. When a read operation occurs, the system only needs to retrieve and compare the pre-stored parity bits, rather than performing complex calculations in real-time. This preliminary action significantly reduces the time penalty for high-precision address error detection.
Data Source
AI summary
It is aimed to detect an error of an address abnormality in a memory. An address error detection information generating unit generates address error detection information for detecting an error relating to an access address for a memory. A control part stores the address error detection information generated by the address error detection information generating unit in the memory at a time of write access. An error detecting part compares the address error detection information generated by the address error detection information generating unit with the address error detection information stored in the memory to detect an error at a time of read access.