Storage Control Device Data Arrival Guarantee
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Solution Overview
Problem
In storage systems with multiplexed controller modules, the reliability of data arrival is compromised due to the presence of relay devices like PCIe switches, which can incorrectly acknowledge data arrival even if data has not reached the destination CPU, leading to potential abnormalities in subsequent data processing stages.
Innovation Solution
The solution involves transmitting write data, additional data, and dummy data through a series of transfer units, with each unit having a buffer area equal to or smaller than the data length, and acknowledging only after the last dummy data has been successfully stored, ensuring that all data has arrived at the destination CPU before acknowledging completion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a relay device (PCIe switch) is introduced to transfer data between CMs, then data transmission capability is improved, but reliability of data arrival guarantee deteriorates because the relay device may incorrectly acknowledge data arrival before the destination CPU actually receives the data
Solution Approach 1:
The invention introduces a preliminary action by having the transmitting CM wait for an explicit arrival notification from the receiving CM before acknowledging data transmission completion. This preliminary waiting step ensures that the data has actually reached the destination CPU, preventing premature acknowledgment. The receiving CM sends an arrival notification when the data is actually stored in its memory, and only after receiving this notification does the transmitting CM send the completion notification to the host device.
2Productivity
If the relay device returns ACK immediately upon storing data in its buffer, then transmission speed is improved, but data reliability deteriorates because the destination CPU may not have received the data yet
Solution Approach 1:
The invention implements a feedback mechanism where the receiving CM provides explicit feedback (arrival notification) to the transmitting CM when the data is actually received and stored in memory. This feedback loop ensures that the transmitting CM has accurate information about data arrival status before sending completion notification. The feedback travels from receiving CM to transmitting CM, and then from transmitting CM to host device, creating a reliable three-stage confirmation process.
3Reliability
If multiple CMs multiplex data to enhance reliability, then system reliability is improved, but communication complexity increases due to the need for coordinated data transmission and acknowledgment among multiple CMs
Solution Approach 1:
The invention segments the data transmission and acknowledgment process into distinct, manageable stages: (1) transmitting CM sends data to relay device, (2) relay device forwards data to receiving CM, (3) receiving CM stores data in memory and sends arrival notification, (4) transmitting CM receives arrival notification and sends completion notification to host device. This segmentation of the communication process into discrete, well-defined steps reduces the complexity of coordinating multiple CMs by making the interaction sequence explicit and manageable.
Data Source
AI summary
A storage control device includes a first processor, a second processor, and transfer units for transferring data from the first processor to the second processor. The first processor receives a write request for writing first data from a first device and sequentially transmits the first data, additional data, and pieces of dummy data. A number of the pieces is same as a number of the transfer units. The first processor notifies the first device of completion of the writing upon receiving an acknowledgement for a last transmitted piece of dummy data. Each transfer unit includes a third processor. The third processor receives the additional data from a preceding processor, and transmits an acknowledgement to the preceding processor upon storing the received additional data. The third processor receives one piece of dummy data from the preceding processor, and transmits an acknowledgement to the preceding processor upon storing the one piece.