Storage Control Device Bypassing CPU Block Device Bottleneck
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Solution Overview
Problem
The existing CPU data operation efficiency on block devices is low due to complex processes requiring multiple instructions to read and write data, as CPUs cannot directly access block devices at byte granularity, necessitating intermediate steps through DRAM.
Innovation Solution
A storage control device with a cache that receives read and write instructions from the CPU, reads or writes data blocks from/to the block device as needed, and returns or writes data to/from the CPU, simplifying operations by bypassing direct CPU-block device interactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the CPU uses multiple operation instructions to read data from a block device into DRAM before accessing it, then the CPU can access data at byte granularity, but the operation process becomes complex and efficiency is reduced
Solution Approach 1:
The patent introduces a storage control device as an intermediary between the CPU and block device. This mediator handles the complex operations of reading data from block devices at block granularity and making it accessible to the CPU at byte granularity, thereby simplifying the CPU's operation process while maintaining fine-grained data access capability
Solution Approach 2:
The patent segments the data access function into two parts: block-level access handled by the storage control device and byte-level access handled by the CPU. This segmentation allows each component to operate at its optimal granularity, improving overall system efficiency while preserving fine-grained access capability
2Ease of operation
If the CPU directly accesses block devices, then the operation process is simplified, but the CPU cannot perform byte-based addressing
Solution Approach 1:
The storage control device is designed with multi-functionality: it can perform block-level data transfer between block devices and DRAM, while also providing byte-granularity address translation and data extraction services for CPU access. This universal design resolves the contradiction between operational simplicity and addressing versatility
3Measurement precision
If the CPU reads data from block device to DRAM using series of instructions, then byte-based data access is enabled, but the number of operation instructions increases
Solution Approach 1:
The storage control device acts as an intermediary that absorbs the complexity of multiple operation instructions. It implements a simplified interface where the CPU issues a single read instruction to access byte-granularity data, while the storage control device internally handles the block-level data transfer and extraction operations
Data Source
AI summary
A data operating method, device, and system are provided and relate to the computer field, so as to resolve a prior-art problem of low efficiency of performing a data operation on a block device by a CPU. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.