Storage Control Units Memory Segmentation
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Solution Overview
Problem
Existing storage systems face inefficiencies in memory sharing due to the need for dedicated programs for each control unit, increased memory access overhead, and reduced reliability due to single-point failures.
Innovation Solution
A storage system with multiple control units, each comprising a processor, first memory for software, a network interface for connecting to a control unit network, and a second memory for data control information and cache data, allowing efficient memory sharing and high reliability through distributed memory management and redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a uniform memory address is allocated to shared memory for each control unit, then memory sharing efficiency is improved, but system reliability deteriorates because the entire system halts when one control unit fails
Solution Approach 1:
The patent divides the unified memory space into separate memory regions for each control unit, with each region having its own address space. This segmentation allows one control unit to fail without affecting the memory access of other control units, thus improving reliability while maintaining memory sharing capabilities through the standardized address interface.
Solution Approach 2:
The patent changes the address space parameter from a fully unified shared address space to a segmented address space where each control unit has its own region. This parameter change enables isolation of failures while preserving the efficiency of standardized address access for memory sharing.
2Speed
If cache memory is implemented in control unit CPU to speed up processing, then processing speed is improved, but memory access overhead increases due to the need to check cache memory on other nodes via communication interface
Solution Approach 1:
The patent extracts the cache memory checking operation from the critical data access path by implementing a cache coherence protocol that allows control units to access memory without explicitly checking remote cache memory first. The cache coherence is maintained through background invalidation signals rather than proactive checking, reducing memory access overhead.
3Manufacturing precision
If dedicated programs are created for each control unit to manage different address ranges, then address management precision is improved, but device complexity and development cost increase
Solution Approach 1:
The patent implements a universal address translation mechanism that works across all control units through standardized address structures. Instead of requiring dedicated programs for each control unit, a single address translation protocol handles all address mappings, reducing program complexity while maintaining precise address management through the unified address space design.
Data Source
AI summary
A storage system having a plurality of control units that perform read control of data stored in a storage and write control of the data, the storage system comprising, each of the plurality of control units has a processor, a first memory connected to the processor and storing software for executing a process of read control and write control, a network interface for connecting to a control unit network that connects each of the plurality of control units, and a second memory connected to the network interface and storing control information of the data subject to read control and write control and cache data of the storage.