Storage Controller BIST via Internal Register Control
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Solution Overview
Problem
Conventional methods for performing built-in self-test (BIST) operations on memory modules within storage controllers face challenges, particularly when there is insufficient space on dense printed circuit boards or when the storage controller is in an enclosed environment, making it difficult to access the test access port (TAP) interface without altering the environment.
Innovation Solution
A method and system that utilize an internal register to initiate the BIST operation, allowing for the selection between using a TAP controller instruction or an internal register control bit to initiate the BIST, and provide access to the BIST operation results via a TAP interface, eliminating the need for a physical TAP interface in some cases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a TAP interface is added to enable BIST operations, then BIST functionality is improved, but board cost and device complexity increase
Solution Approach 1:
The patent extracts the TAP interface requirement by implementing BIST through internal register control bits instead of requiring external TAP interface pins. The control bit is taken from the internal register and used to initiate BIST, eliminating the need for physical TAP interface connections on the board.
Solution Approach 2:
The patent introduces an intermediary mechanism where the internal register control bit acts as a mediator between the processor and the BIST controller. Instead of directly accessing TAP interface, the processor sets a control bit in the internal register, which then triggers the BIST operation through the intermediary register system.
2Adaptability or versatility
If a TAP interface is provided for BIST access, then BIST operation capability is improved, but ease of operation in enclosed environments deteriorates
Solution Approach 1:
The patent removes the requirement for external TAP interface access by implementing BIST initiation through internal register control bits. This extraction of the TAP interface dependency allows BIST operations to function correctly even when the interface is inaccessible in enclosed rack environments.
Solution Approach 2:
The system performs self-service by allowing the processor to initiate BIST operations through internal register control without requiring external intervention or physical access to TAP interfaces. The BIST controller is triggered automatically when the control bit is set in the internal register.
3Ease of operation
If internal register control bit is used to initiate BIST, then ease of operation is improved, but ability to access BIST results via TAP interface deteriorates
Solution Approach 1:
The patent implements multi-functionality by designing the internal register to serve dual purposes: it contains both the control bit for initiating BIST operations and the status bit for indicating completion. The same internal register system handles both initiation and status indication, eliminating the need for separate TAP interface access for results.
Data Source
AI summary
A storage controller including a first controller. The first controller includes a memory module, a test access port controller, the test access port controller configured to control a built in self-test operation on the memory module, and a register configured to store a first instruction. In response to the storage controller detecting a test access port interface being accessible to the storage controller, the test access port controller is configured to control the built in self-test operation on the memory module of the first controller by having either (i) a second instruction sent from the test access port controller to the first controller or (ii) the first instruction sent from the register to the first controller. The first controller is configured to perform the built in self-test operation on the memory module in response to having received the first instruction or having received the second instruction.