Storage Controller Buffer Context Backup Circuit Power Management
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Solution Overview
Problem
Existing storage devices face challenges in efficiently managing power modes, particularly in reducing power down exit time and enhancing performance due to the need for reconstructing buffer allocation information during power up, which increases processing time and power consumption.
Innovation Solution
A storage device with a nonvolatile memory and a storage controller that includes a buffer memory, first and second volatile memories in different power domains, and a buffer context backup circuit to perform context backup and restoration operations, allowing for efficient power mode transitions by compressing and decompressing buffer allocation information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If buffer allocation information is stored in volatile memory and power is blocked during power down mode, then power consumption is reduced, but the buffer allocation information is lost and must be reconstructed during power up, increasing exit time
Solution Approach 1:
The patent applies preliminary action by compressing and storing buffer allocation information in the second volatile memory (power on domain) before power down mode is activated. This pre-stored compressed information is then quickly decompressed and restored to the first volatile memory during power up, eliminating the need for time-consuming reconstruction and reducing power down exit time while maintaining low power consumption during the power down state.
2Use of energy by moving object
If buffer allocation information is reconstructed during power up, then power consumption during power down is reduced, but processing time and power consumption during power up increase
Solution Approach 1:
The patent applies copying by creating a compressed copy of the buffer allocation information and storing it in the second volatile memory (power on domain) before power down. This copy serves as a backup that can be quickly restored during power up without needing to reconstruct the original information, thereby maintaining high processing speed during power up while achieving low power consumption during power down mode.
3Loss of time
If a second volatile memory is added to store backup information, then power down exit time is reduced, but device complexity increases
Solution Approach 1:
The patent applies the nested doll principle by implementing a hierarchical memory structure where the first volatile memory (power off domain) is used during active operation, and the second volatile memory (power on domain) serves as a nested backup storage for compressed buffer allocation information. This nested arrangement allows quick restoration during power up by accessing the pre-stored compressed data in the second memory, reducing power down exit time while organizing the complexity in a structured, manageable way.
Data Source
AI summary
A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a buffer memory, a first volatile memory, a second volatile memory, a processor and a buffer context backup circuit. The buffer memory temporarily stores read data and write data. The first and second volatile memories are included in different power domains. The processor generates buffer allocation information, stores the buffer allocation information in the first volatile memory, and controls an access to the buffer memory based on the buffer allocation information. The buffer context backup circuit performs a context backup operation to back up the buffer allocation information from the first volatile memory to the second volatile memory when entering a power down mode and performs a context restoring operation to restore the buffer allocation information from the second volatile memory to the first volatile memory when exiting from the power down mode.