Data Storage Controller Buffer State Segmentation
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Solution Overview
Problem
Data storage devices face inefficiencies in processor overhead and operational performance due to the need for continuous buffer state checks before processing access requests, leading to delays in write and read operations.
Innovation Solution
Implementing a controller with multiple memory controllers that can transmit access commands to nonvolatile memory devices regardless of the buffer state, allowing for independent determination of buffer states and optimized command processing by each memory controller, thereby reducing processor overhead and improving operational performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor continuously checks buffer state before processing access requests, then data integrity is ensured, but processor overhead increases and operational performance deteriorates
Solution Approach 1:
The controller is segmented into a processor and multiple independent memory controllers. The processor handles high-level access requests while memory controllers handle low-level buffer state checks and command execution. This segmentation allows the processor to avoid continuous buffer state checking, reducing overhead and improving operational performance while maintaining data integrity through distributed checking at the memory controller level.
2Reliability
If the processor waits for buffer state verification before transmitting access commands, then buffer overflow is prevented, but processing delays increase
Solution Approach 1:
Memory controllers perform preliminary buffer state checks and command validation before executing access commands, rather than waiting for processor verification. This preliminary action at the memory controller level prevents buffer overflow while allowing the processor to transmit commands without delay, thus eliminating processing delays while maintaining reliability.
3Measurement precision
If the processor manages all access requests sequentially with buffer state checks, then control accuracy is maintained, but processing speed decreases
Solution Approach 1:
Memory controllers act as intermediaries between the processor and nonvolatile memory devices. They receive access commands from the processor, independently verify buffer states, and execute commands with precise control. This intermediary role maintains control accuracy while enabling parallel processing of multiple access requests, thus increasing processing speed without sacrificing precision.
Data Source
AI summary
A data storage device includes nonvolatile memory devices coupled to a plurality of channels; and a controller including a processor, a buffer and memory controllers which are respectively coupled to the channels, wherein the processor transmits a first access command to a first memory controller in response to a first access request from a host device, regardless of a state of the buffer, and wherein the first memory controller controls an internal operation of a first nonvolatile memory device by determining the state of the buffer, in response to the first access command.