Storage Controller Processor Cache Bandwidth Management
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Solution Overview
Problem
The existing storage apparatuses face performance degradation due to increased bandwidth consumption of primary storage devices as data transfer volumes rise, especially when accessing cache areas across clusters, which is exacerbated by the limited capacity of typical processor caches.
Innovation Solution
A storage system that employs a processor core circuit with a cache and a primary storage device, where data transfer decisions are made based on command types and retention storage devices, utilizing the processor cache to reduce bandwidth consumption by strategically storing user data and using it as a transfer buffer between clusters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is transferred through primary storage devices in multiple clusters using two-stage communication, then cache access is enabled across clusters, but bandwidth consumption of primary storage devices increases significantly
Solution Approach 1:
The patent introduces a dedicated cache memory in the storage controller as an intermediary buffer between the host interface and primary storage devices. This mediator cache handles data transfer operations, reducing the need for primary storage devices to directly participate in cross-cluster communications and thereby reducing their bandwidth consumption.
Solution Approach 2:
The patent divides the storage system into multiple independent clusters, each with its own storage controller and primary storage devices. This segmentation allows local data processing within clusters, reducing the need for inter-cluster primary storage device communications and lowering overall bandwidth consumption.
2Productivity
If primary storage devices are used for caching user data, then data transfer performance is improved, but bandwidth limitations of primary storage devices constrain overall system performance
Solution Approach 1:
The patent makes the processor cache multi-functional by using it not only for general processing purposes but also as a dedicated cache for user data and transfer buffer. This allows the system to leverage existing high-speed cache resources for data transfer operations, bypassing the bandwidth limitations of primary storage devices.
Solution Approach 2:
The patent changes the operational parameters of the storage system by utilizing the processor cache with capacities in the gigabyte range, which is significantly larger than typical processor caches. This parameter change enables the system to achieve both high-speed access and large cache capacity, overcoming the bandwidth and capacity limitations of traditional primary storage devices.
3Ease of manufacture
If general-purpose processors are used instead of dedicated LSI, then component integration and cost are improved, but direct access to primary storage devices across clusters is restricted
Solution Approach 1:
The patent introduces a storage controller as an intermediary layer between the general-purpose processor and primary storage devices. This mediator provides the necessary control functions and data access capabilities that would otherwise require dedicated LSI, allowing the use of general-purpose processors while maintaining efficient storage access.
Solution Approach 2:
The patent enables the storage controller to autonomously manage data caching and transfer operations using the processor cache, without requiring complex inter-cluster direct access mechanisms. This self-service capability simplifies the overall system architecture while maintaining functionality.
Data Source
AI summary
An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device.