Storage Controller Cache Table Consistency During Partial Activation

The patent applies preliminary action by having the master CM pre-acquire cache tables and store them in a shared memory region before slave CMs are activated. When slave CMs are activated, they directly acquire the pre-prepared cache tables from shared memory, ensuring consistent acquisition states without timing conflicts. This resolves the contradiction by eliminating the race condition that occurs when multiple CMs simultaneously attempt to acquire cache tables from the same memory region.

The patent applies segmentation by dividing the memory space into distinct, non-overlapping regions: a shared memory region for control information and separate cache memory regions for each CM's cache tables. The master CM writes control information to the shared memory region, while slave CMs acquire cache tables from this shared region without overlap. This spatial segmentation eliminates the data destruction risk while preserving dynamic configuration capability, as the master CM can still update control information in the shared region without affecting the slave CMs' cache tables.

The patent introduces an intermediary mechanism: a shared memory region that acts as a mediator between the master CM and slave CMs for cache table acquisition. The master CM writes cache tables to this intermediary shared region, and slave CMs read from it, ensuring that all CMs acquire consistent cache table states without direct interaction or timing conflicts. This intermediary mechanism enables simultaneous CM activation while maintaining configuration consistency, resolving the contradiction between productivity and manufacturing precision.