Storage Controller Cache Parity Alignment for Write Speed
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Solution Overview
Problem
Conventional storage controlling systems face inefficiencies in write-through operations due to mismatched data lengths and the need for time-consuming ECC generation and processing, which hinders stability and speed in applications requiring reliable operation.
Innovation Solution
A storage controlling system that includes a cache memory and a controller, which receives writing instructions, decides whether data is cached, updates the data in the cache memory, and outputs it to the storage apparatus in units of parity generation, eliminating the need for read-modify-write operations and enhancing writing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write-through technology is employed to ensure data consistency between storage apparatus and cache memory, then reliability is improved, but writing process speed deteriorates due to time-consuming read-modify-write operations
Solution Approach 1:
The system pre-loads data from the storage apparatus into the cache memory before write operations are needed. This preliminary action ensures that when write operations occur, the data is already available in the cache, eliminating the need for time-consuming read-modify-write operations and maintaining high writing speed while ensuring data consistency
Solution Approach 2:
The patent introduces a storage controlling apparatus as an intermediary between the host apparatus and the storage apparatus. This intermediary manages the cache memory and coordinates write operations, allowing it to optimize data flow and eliminate redundant read-modify-write operations while maintaining data consistency across the system
2Productivity
If data is processed in units of ECC generation length to improve writing speed, then productivity is improved, but data length mismatch causes operational instability
Solution Approach 1:
The patent segments data into units of ECC generation length for parallel processing and caching operations. By dividing data into these standardized segments, the system can efficiently process multiple units simultaneously while ensuring each segment maintains proper alignment with ECC boundaries, thus achieving high writing speed without compromising data integrity
Solution Approach 2:
The system dynamically adjusts data processing parameters to match ECC generation length requirements. By changing the data segmentation and caching parameters to align with ECC boundaries, the system optimizes writing speed while ensuring compatibility with error correction requirements, eliminating operational instability caused by length mismatches
Data Source
AI summary
A storage controlling system, coupled to a storage apparatus including storage disk devices, receives writing target data, generates a parity in units of parity generation of a given length for the data, and stores the data and parity into the devices. The system includes a cache memory and controller. The controller includes: a reception section receiving a writing instruction including the writing target data and information for specifying a target sector to write the data to; a decision section deciding whether processing target data is held in the cache memory, the processing target data including at least one unit of parity generation that includes sector data stored in the sector and fraction data other than the sector data; and a writing processing section updating, when the processing target data is in the cache memory, the data based on the instruction and outputting the post-update data as the writing target data to the apparatus.