Storage Controller Clocking for Per-Channel Memory Interface Speed
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Solution Overview
Problem
The performance and throughput of solid-state storage devices are limited by PCB layout and storage capacity requirements, particularly in enterprise applications, due to increased insertion loss, crosstalk, and distortions in longer PCB traces, which degrade interface speed and limit maximum interface speed.
Innovation Solution
A controller with a processor and clock generator that generates clock signals with varying frequencies for multiple communication channels based on values stored in registers, allowing flexible interface speed settings to optimize communication across different channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more non-volatile memories are integrated onto the PCB to achieve higher storage capacity, then storage capacity increases, but PCB trace length increases causing increased insertion loss, crosstalk and distortions that degrade interface speed
Solution Approach 1:
The patent applies dynamics by making the interface speed configurable and adjustable for each communication channel individually. The controller can dynamically set different interface speeds based on the actual PCB trace characteristics and device loading conditions of each channel, rather than using a fixed uniform speed across all channels. This allows the system to adapt to varying physical conditions while maintaining optimal performance.
Solution Approach 2:
The patent implements local quality by allowing each communication channel to have its own independently configurable interface speed. Channels with shorter PCB traces and lighter device loading can operate at higher speeds, while channels with longer traces and heavier loading operate at lower speeds. This localized optimization resolves the contradiction by tailoring the interface speed to the specific physical characteristics of each communication path.
2Device complexity
If the controller communicates at the same interface speed through multiple communication channels, then simplicity is maintained, but the maximum interface speed is limited by the longest physical trace with the heaviest device loading
Solution Approach 1:
The patent applies parameter changes by introducing configurable interface speed parameters for each communication channel. The controller includes registers that store speed configuration values, and a clock generator that produces clock signals with frequencies determined by these registered values. This allows the system to change the operational parameters (interface speeds) of different channels independently, enabling each channel to operate at its optimal speed based on physical characteristics rather than being constrained by the slowest channel.
Data Source
AI summary
Disclosed herein is a new technique for providing a storage controller with variable interface communication speeds to allow the storage controller to set different communication speeds and frequencies for different communication channels between the storage controller and respective memories. A controller comprises: a processor; registers; and a clock generator configured to generate clock signals respectively for multiple communication channels based on values stored in the registers. The controller is configured to communicate with non-volatile memories through the communication channels respectively using the clock signals.