Storage Controller Clock Frequency Scaling

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Solution Overview

Problem

Conventional storage controllers lack the ability to scale their clock signal during active states, leading to power inefficiencies due to constant peak frequency operation, which does not adapt to varying data traffic patterns, resulting in wasted power savings.

Innovation Solution

A storage controller system that includes a clock generator and pipeline stages with gearboxes that adjust clock signals based on performance metrics such as throughput and pending commands, allowing for frequency scaling to reduce power consumption during non-peak data traffic periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the storage controller runs at peak frequency during active states, then it can accommodate the highest data traffic patterns, but it results in power inefficiencies and wasted power when data traffic is lower

Engineering Contradiction:
Improvedata traffic handling capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The storage controller dynamically adjusts its clock signal frequency based on actual data traffic conditions. The system transitions from a static peak frequency operation to a dynamic frequency scaling mechanism that adapts to varying workload demands, thereby reducing power consumption during low-traffic periods while maintaining peak performance when needed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameter of clock signal frequency from a fixed peak value to a variable parameter that scales according to data traffic intensity. This allows the storage controller to optimize the trade-off between performance and power consumption by adjusting the frequency parameter in response to changing operational conditions

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If the storage controller lacks the capability to scale its clock signal, then the device complexity remains low, but it cannot adapt to varying data traffic patterns resulting in power inefficiencies

Engineering Contradiction:
Improveadaptability to data traffic patternsVSAvoidclock signal scaling capability
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The storage controller implements a feedback mechanism that monitors data traffic conditions and uses this information to adjust the clock signal frequency. This feedback loop enables the system to automatically adapt to varying traffic patterns without requiring complex external control, achieving adaptability through intelligent response to operational conditions

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The storage controller performs self-adjustment of its clock frequency based on its own operational needs and observed traffic patterns. The system serves itself by autonomously scaling its performance characteristics without requiring external intervention, thereby achieving adaptability while minimizing additional system complexity

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11768531B2Power management for storage controllers
Publication Date: 2023.09.26 SANDISK TECHNOLOGIES LLC
  • US11768531B2 patent drawing
  • US11768531B2 patent drawing
  • US11768531B2 patent drawing

AI summary

A storage controller includes a plurality of pipeline stages configured to process data. A system clock signal is received that has a system frequency and at least one performance metric is determined for one or more pipeline stages of the plurality of pipeline stages. A first clock signal is generated having a first frequency for operation of a first pipeline stage of the plurality of pipeline stages. Based at least in part on the at least one determined performance metric, a second clock signal is generated having a second frequency for operation of a second pipeline stage of the plurality of pipeline stages. The second frequency is less than the system frequency and may also differ from the first frequency.