Storage Controller Command Processing for Processor Idle Time Reduction

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Solution Overview

Problem

In general storage devices, varying processor execution times for different commands lead to significant processor idle times, resulting in wasted resources due to inefficient utilization of processor resources.

Innovation Solution

A command processing method that categorizes I/O commands based on a processor effort index, allowing for dynamic clock frequency adjustment and timer management to integrate idle times and optimize processor usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If commands are executed in the order they are received from the command queue, then command execution simplicity is maintained, but processor idle times increase significantly due to varying processor execution times and data transmission times

Engineering Contradiction:
Improvecommand execution simplicityVSAvoidprocessor idle time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent segments commands into different groups based on their processor effort index (ratio of processor execution time to data transmission time). By categorizing commands into groups with similar characteristics, the system can optimize execution strategies for each group, reducing overall processor idle time while maintaining manageable execution complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts clock frequency based on the processor effort index of executing commands. When processor execution time exceeds data transmission time, the clock frequency is lowered to match the data transmission rate, eliminating processor idle time. This dynamic adjustment resolves the contradiction by adapting execution speed to actual workload requirements.

Inventive Principle:
Principle #15Dynamics

2Speed

If clock frequency is maintained at maximum level, then processing speed is maximized, but power consumption increases during periods when processor would otherwise be idle

Engineering Contradiction:
Improveprocessor speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic clock frequency adjustment based on the processor effort index. When the index indicates that processor execution time is less than data transmission time, the clock frequency is lowered before execution completes, reducing power consumption during periods when the processor would otherwise be idle. This resolves the contradiction by matching processing speed to actual computational requirements.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter dynamically based on command characteristics. By adjusting this critical parameter according to the processor effort index, the system optimizes the balance between processing speed and power consumption, maintaining high speed when needed and reducing consumption when processors would be idle.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If commands with varying processor execution times are processed sequentially, then command processing simplicity is maintained, but processor resource utilization efficiency decreases

Engineering Contradiction:
Improveprocessing complexityVSAvoidprocessor resource utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the command stream into groups based on processor effort index thresholds. This segmentation allows the system to apply different execution strategies to different groups, improving overall processor utilization without requiring complex real-time decision-making for individual commands, thus maintaining acceptable processing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary classification of commands into groups based on their processor effort index before execution. This preliminary action allows the system to prepare execution strategies in advance, improving processor resource utilization without adding complexity during actual command execution.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10372379B2Command processing method and storage controller using the same
Publication Date: 2019.08.06 SHENZHEN EPOSTAR ELECTRONICS LTD
  • US10372379B2 patent drawing
  • US10372379B2 patent drawing
  • US10372379B2 patent drawing

AI summary

A command processing method and a storage controller using the same are provided. The command processing method includes: receiving a plurality of I/O commands; categorizing the I/O commands into a plurality of groups according to a processor effort index of the I/O commands; selecting a first group from the groups, resetting a timer and obtaining an expiration time corresponding to the first group according to the I/O commands of the first group, and executing the I/O commands of the first group; and selecting a second group from the groups and resetting the timer when the expiration time of the first group expires, wherein when the processor effort index of the first group is less than a threshold, a clock frequency of the processor is lowered before the expiration time expires.