Storage Controller Completion Timing Using Host Latency
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Solution Overview
Problem
Existing storage systems face inefficiencies due to increased host overhead when managing data with non-volatile memory express (NVMe) interfaces, leading to delayed processing of host-managed data.
Innovation Solution
A storage controller that manages completion timing by determining when to write completion signals based on latency information provided by the host, using a command manager and DMA engine to process commands and data transfers efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the host manages processed data with NVMe interface, then data processing capability is improved, but host overhead increases and delays other processes
Solution Approach 1:
The patent extracts the completion timing management function from the host and transfers it to the storage controller. The storage controller autonomously determines when to write completions to the completion queue based on latency information, removing this overhead burden from the host and allowing the host to proceed with other processes without delay.
2Speed
If completion is written immediately after processing, then processing speed is improved, but host overhead increases
Solution Approach 1:
The storage controller performs self-service by autonomously managing completion timing without host intervention. It uses the latency information from commands to independently determine when to write completions, eliminating the need for host management and reducing host overhead while maintaining efficient processing.
3Ease of operation
If the storage controller manages completion timing autonomously, then host overhead is reduced, but control precision requirements increase
Solution Approach 1:
The latency information included in each command serves as feedback that guides the storage controller's completion timing decisions. The controller uses this feedback to precisely determine when to write completions, achieving accurate timing control autonomously without requiring complex host management.
Data Source
AI summary
A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.


