Storage Controller DMA Engine Bypassing Buffer Memory
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in efficiently managing read requests from host devices, particularly in reducing read latency and improving performance by minimizing the use of buffer memory.
Innovation Solution
The proposed solution involves a storage controller with a buffer memory, an address manager, and a direct memory access (DMA) engine. This controller processes read requests by storing mapping information in a translation table, setting a destination address for read data to a virtual address, and translating this address to the host address, thereby bypassing the need for buffer memory in data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read data is transmitted through buffer memory, then data transmission reliability is improved, but read latency increases and performance deteriorates
Solution Approach 1:
The patent extracts the buffer memory component from the data transmission path by implementing direct memory-to-host transmission. The DMA engine directly transmits read data from non-volatile memory to the host device, eliminating the intermediate buffer memory step while maintaining transmission reliability through error correction codes and data integrity checks.
Solution Approach 2:
The patent introduces a virtual address as an intermediary mechanism to enable direct transmission. The address manager translates host addresses to virtual addresses, allowing the DMA engine to directly access and transmit data without physical buffer memory, while the translation table maintains the mapping relationship for reliable data delivery.
2Reliability
If buffer memory is used for data transmission, then data integrity is improved, but system performance and efficiency deteriorate
Solution Approach 1:
The patent removes buffer memory from the transmission path and replaces it with direct DMA transmission. Data integrity is maintained through error correction codes (ECC) applied during the direct transmission process, while performance improves by eliminating buffer write/read operations and reducing memory access latency.
Solution Approach 2:
The patent substitutes the mechanical buffer memory system with a virtual address translation system. The address manager and translation table provide the necessary data routing and integrity management functions that previously required physical buffer memory, enabling faster direct transmission while maintaining data integrity through software-based address management.
3Device complexity
If traditional address mapping is used, then address management is simplified, but transmission speed and efficiency are reduced
Solution Approach 1:
The patent performs address translation in advance by maintaining a translation table that maps host addresses to virtual addresses. The address manager pre-processes address mapping requests and stores the mappings, enabling the DMA engine to perform rapid address translation during data transmission without real-time computation delays.
Solution Approach 2:
The patent introduces the virtual address as an intermediary layer between host addresses and physical memory addresses. This virtual addressing mechanism enables efficient address translation through the translation table, allowing fast direct memory access while maintaining simplified address management through the address manager's translation operations.
Data Source
AI summary
Provided is an operating method of a storage controller that includes a buffer memory, an address manager, and a direct memory access (DMA) engine and controls a non-volatile memory device. The operating method includes receiving, from an external host device, a read request including a host address, storing, by an address manager in response to the read request, mapping information about the host address and a command identifier corresponding to the read request in a translation table, setting, by the DMA engine, a destination address of read data corresponding to the read request to a virtual address corresponding to the command identifier, and transmitting the read data to the virtual address, and translating, by the address manager based on the translation table, the destination address of the read data from the virtual address to the host address.