Storage Controller DMA on ATC Misses Using Host Memory Buffers
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Solution Overview
Problem
The performance of storage systems is degraded due to increased cache miss rates and variable update latency in address translation caches (ATCs) when accessing non-volatile memory devices, as the number of virtual addresses to be translated increases, exceeding the limited size of the ATC.
Innovation Solution
A storage device with an address translation cache that performs direct memory access to a host-specific memory buffer when a cache miss occurs, transmitting an exceptional completion queue with an indicator to the host, and shares index information in advance to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is read based on the non-volatile memory device, then performance of the storage system is improved, but the number of virtual addresses to be translated increases and ATC miss rate increases
Solution Approach 1:
The host stores index information corresponding to virtual addresses in its memory in advance. When the storage device needs to translate a virtual address and experiences an ATC miss, it performs a binary search on the pre-stored index information to quickly locate the corresponding physical address, avoiding the need to maintain a larger ATC.
Solution Approach 2:
The patent extracts the address translation information from the ATC and stores it separately in the host's memory as index information. This separates the translation data storage function from the ATC, allowing the ATC to remain small while still enabling efficient address translation through external index searching.
2Reliability
If the size of the ATC is increased to reduce cache miss rate, then address translation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary mechanism where the host's memory serves as an external index database. The storage device performs binary search on this external index information when ATC miss occurs, acting as a mediator between the limited ATC and the full address translation requirements, thereby maintaining high translation accuracy without increasing ATC size.
3Reliability
If traditional address translation is performed through IOMMU or CPU, then address translation completeness is ensured, but processing speed decreases
Solution Approach 1:
Index information is prepared in advance and stored in the host's memory. When address translation is needed, the storage device can directly search this pre-prepared index using binary search, eliminating the need for IOMMU or CPU intervention and significantly accelerating the translation process while maintaining completeness.
Solution Approach 2:
The storage device performs address translation autonomously by searching the index information stored in host memory using binary search. This self-service mechanism eliminates dependency on external IOMMU or CPU resources, improving translation speed while ensuring complete and accurate address mapping.
Data Source
AI summary
A storage device, a storage system and an operating method of the storage device are provided. The storage device connected to a host comprises a storage controller including an address translation cache that translates a virtual address received with a command from the host into a physical address, wherein the storage controller stores index information on a host specific memory buffer (SMB) in the host in advance, performs direct memory access to the virtual address for the host SMB when a cache miss occurs in the address translation cache, and transmits an exceptional completion queue (CQ) including an indicator to the host when the direct memory access is completely performed.