Storage Controller DMA Path Switching for Low-Latency Reads
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Solution Overview
Problem
Current storage devices experience high read latency and require large buffer sizes, which increase costs and reduce performance, especially in random read operations.
Innovation Solution
A controller that selectively performs either a 1-stage or 2-stage DMA operation based on the read path attribute, allowing direct data transfer from the error correction circuit's output buffer to the host device, thereby optimizing read operations and reducing buffer size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a traditional 2-stage DMA operation is used for all read requests, then data can be buffered and transferred systematically, but read latency increases and buffer size requirements increase
Solution Approach 1:
The patent applies dynamics by making the DMA operation mode adjustable and adaptable based on request attributes. The controller dynamically selects between 1-stage and 2-stage DMA operations depending on whether the read request is sequential or random, allowing the system to optimize performance for different access patterns rather than using a fixed approach
Solution Approach 2:
The patent segments the DMA operation into two distinct modes (1-stage and 2-stage) that can be selectively applied. By dividing the read operation handling into different pathways based on request type, the system can choose the most efficient segment for each specific case, reducing overall latency and buffer requirements
2Productivity
If a 1-stage DMA operation is used for all read requests, then read latency is reduced, but it is not suitable for all read request types particularly random reads
Solution Approach 1:
The system dynamically adjusts the DMA operation mode based on the attributes of each read request. For sequential reads, it uses 1-stage DMA for high speed, while for random reads, it uses 2-stage DMA for proper buffering, making the system adaptable to different access patterns
Solution Approach 2:
The patent applies local quality by treating different types of read requests differently. Instead of applying a uniform DMA mode to all reads, it applies the appropriate DMA mode (1-stage or 2-stage) locally based on the specific characteristics of each read request, optimizing performance for each case
3Loss of time
If sequential reads are performed directly from the output buffer, then read latency is reduced, but buffer memory size must be sufficiently large to handle all cases
Solution Approach 1:
The controller dynamically determines the DMA operation mode based on read request attributes, adjusting buffer usage accordingly. For sequential reads, it uses 1-stage DMA that requires less buffer memory, while for random reads, it uses 2-stage DMA that utilizes the buffer appropriately, optimizing both latency and memory usage
Data Source
AI summary
An operating method of a storage device is provided. The operating method includes: receiving a host read command from a host device; identifying whether a read path corresponding to the host read command corresponds to a first direct memory access (DMA) read path; and directly outputting, by a host DMA manager, read data stored in an output buffer of an error correction circuit to the host device based on the read path corresponding to the first DMA read path.