Storage Controller DMA Timing Adjustment for QOS Compliance
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Solution Overview
Problem
Existing storage devices face challenges in efficiently managing direct memory access (DMA) operations across multiple non-volatile memory devices connected via the same channel, leading to delays in processing new commands and potential violations of quality of service (QOS) requirements.
Innovation Solution
The storage device incorporates a memory controller with a DMA engine that generates commands for DMA operations and adjusts the output time intervals between these commands for non-volatile memory devices connected to the same channel, effectively distributing the DMA intervals to reduce delays and improve QOS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA operations are performed sequentially on multiple non-volatile memory devices connected via the same channel, then data transfer efficiency is improved, but delay time in processing new host read commands increases
Solution Approach 1:
The patent segments the DMA operation timeline by introducing distinct first and second time intervals between DMA operations on different memory devices. This temporal segmentation allows the system to complete DMA transfers while creating dedicated windows for processing new host read commands, thereby resolving the contradiction between data transfer efficiency and command processing speed.
2Productivity
If DMA operations are performed on multiple non-volatile memory devices connected via the same channel, then bandwidth utilization is improved, but quality of service requirements may be violated
Solution Approach 1:
The patent applies preliminary action by pre-establishing the first time interval between DMA operations before new host read commands arrive. This predetermined timing ensures that QOS requirements are met in advance, allowing the system to maintain both high bandwidth utilization through DMA operations and reliable service quality by guaranteeing command processing deadlines.
3Speed
If output time interval between DMA commands is reduced, then command processing speed is improved, but DMA operation conflicts on the same channel increase
Solution Approach 1:
The patent introduces dynamic timing adjustment by defining the first time interval based on the actual output time interval between DMA commands. This dynamic approach allows the system to optimize command processing speed while automatically adjusting to prevent DMA conflicts on the same channel, balancing performance with operational simplicity.
Data Source
AI summary
A storage device includes a memory controller, a buffer memory, and a memory device including a plurality of non-volatile memory devices connected to the memory controller via an identical channel. The memory controller is configured to generate a first command for performing a first DMA operation and a second command for performing a second DMA operation, adjust an output time interval between a first output time point of the first command with respect to a first non-volatile memory device among the plurality of non-volatile memory devices and a second output time point of the second command with respect to a second non-volatile memory device among the plurality of non-volatile memory devices, and is configured to add a time interval corresponding to the output time interval between an end time point of the first DMA operation corresponding to the first command and a start time point of the second DMA operation corresponding to the second command.