Storage Controller DMA Data Transfer for Consistency
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Solution Overview
Problem
In storage systems with general-purpose controllers, duplicating data to ensure consistency can lead to increased processing loads on processors, potentially deteriorating system performance.
Innovation Solution
A storage system design that includes multiple controllers with a DMA unit for direct memory access, allowing data to be sequentially transferred from a buffer region to cache regions without passing through other buffer regions, thereby managing processing loads and ensuring data consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is duplicated in each controller's buffer region and then transferred through other buffer regions to ensure consistency, then data consistency is secured, but the processing load of the controller on the processor increases
Solution Approach 1:
The patent divides the data transfer process into two distinct phases: first, the receiving controller transfers data directly from its buffer region to the cache region of the duplicating controller via DMA; second, the duplicating controller independently distributes data to other controllers' cache regions. This segmentation eliminates the need for processors to handle intermediate buffer transfers, reducing processing load while maintaining data consistency.
Solution Approach 2:
The patent introduces cache regions as intermediary storage areas between controllers. Instead of having processors manage complex buffer-to-buffer transfers across multiple controllers, data is first placed in cache regions which then serve as distribution points. This intermediary mechanism simplifies the transfer path and reduces processor involvement in data duplication operations.
2Reliability
If data is transferred through other buffer regions to ensure data consistency across controllers, then data consistency is maintained, but the processing load on the controller increases
Solution Approach 1:
The transfer process is segmented into distinct responsibilities: the receiving controller handles the initial transfer to the duplicating controller's cache region, and the duplicating controller handles subsequent distribution to other controllers. This segmentation simplifies the overall process by eliminating complex multi-buffer transfer sequences and reducing the need for intricate coordination protocols.
3Productivity
If data is sequentially transferred from buffer region to cache regions without passing through other buffer regions, then the processing load on the processor is reduced, but data consistency must be properly secured
Solution Approach 1:
The receiving controller performs the preliminary action of transferring data directly to the duplicating controller's cache region before other controllers need the data. This preliminary transfer establishes a reliable source copy that can then be distributed to other controllers, ensuring data consistency is secured before distribution begins, while allowing parallel processing operations to proceed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively secures data consistency while reducing the processing load on controllers, enhancing the overall performance of the storage system.
Implementation Method 1
a DMA (Direct Memory Access) unit that can directly access a memory and can communicate with other controllers
Data Source
AI summary
An object of the present invention is to properly secure the consistency of data while suppressing a processing load of a controller on a processor. A storage system includes a plurality of controllers and an HCA that can directly access a memory and can communicate with the controllers. The controller includes a CPU, and a memory having a buffer region into which data is temporarily stored and a cache region into which data is cached. In the case where new data according to a write request is stored into the buffer region, the CPU of the controller sequentially transfers the new data to the cache regions using the HCA without passing through the other buffer regions.