Storage Controller ECC Scheduling for Variable NAND Error Levels
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Solution Overview
Problem
Existing semiconductor memory systems face challenges in efficiently correcting errors of varying levels without increasing chip area or decreasing throughput, as they require separate error processing devices for low and high error levels.
Innovation Solution
A storage controller with an ECC scheduler and multiple decoders of different error correction capabilities, where the scheduler selects the appropriate decoder based on the error level of the data, allowing shared access to all NAND flash memories and optimizing decoder usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple error processing devices are implemented to cope with both low and high error levels, then error correction capability is improved, but chip area increases
Solution Approach 1:
The patent implements a universal error processing device that can dynamically adapt its error correction capability based on the error level of incoming data. The device switches between low error correction mode (for initial manufacturing errors) and high error correction mode (for errors after repeated use), allowing a single device to perform multiple error correction functions that would traditionally require separate dedicated devices for each error level.
Solution Approach 2:
The error processing device incorporates dynamic switching capability between different error correction modes. The device can change its operational state based on real-time error level detection, transitioning from a low-capacity correction mode to a high-capacity correction mode when high-level errors are detected, and vice versa. This dynamic adaptation allows the system to maintain high reliability across different scenarios without requiring parallel static error processing devices.
2Reliability
If multiple error processing devices are implemented to cope with both low and high error levels, then error correction capability is improved, but throughput decreases
Solution Approach 1:
The universal error processing device handles both low and high error level scenarios sequentially, eliminating the need for multiple parallel error processing devices. By consolidating error correction functions into a single adaptable device, the patent maintains high throughput while ensuring comprehensive error correction capability across different error levels.
Solution Approach 2:
The dynamic mode switching enables the error processing device to optimize its processing speed based on the error level. In low error correction mode, the device operates at higher throughput for routine errors, while in high error correction mode, it processes errors more intensively when needed. This dynamic adjustment maintains overall system throughput while providing high error correction capability when required.
3Area of stationary object
If a single error processing device is used for both low and high error levels, then chip area is reduced, but error correction capability for high level errors decreases
Solution Approach 1:
The error processing device dynamically adjusts its correction capability based on the detected error level. When high-level errors are detected (indicating repeated use scenarios), the device switches to high error correction mode, activating enhanced correction algorithms and resources. For low-level errors (initial manufacturing scenarios), it operates in low correction mode with reduced processing overhead. This dynamic adaptation ensures high error correction capability is available when needed without permanently allocating the resources required for a dedicated high-capacity device.
Solution Approach 2:
The device changes its operational parameters based on error level detection. It adjusts correction thresholds, algorithm complexity, and processing intensity dynamically. When transitioning from low to high error correction mode, the device modifies its internal parameters to enhance correction capability, effectively transforming a single device into a multi-capability error processing system that can match the performance of multiple dedicated devices.
Data Source
AI summary
An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.