Storage Controller Encoding for Adjacent Wordline Interference

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Solution Overview

Problem

As the degree of integration in semiconductor memory devices increases, threshold voltage distributions of memory cells can be disrupted due to wordline interference between adjacent memory cells, affecting data reliability in flash memory devices.

Innovation Solution

A storage device and method that encode data to be programmed into a target wordline based on the program state of adjacent wordlines, ensuring that data written into specific portions of memory cells satisfies specific conditions to minimize interference and maintain reliable threshold voltage distributions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the degree of integration of memory cells is increased, then the storage capacity is improved, but the threshold voltage distribution is disrupted due to wordline interference

Engineering Contradiction:
Improvestorage capacityVSAvoidthreshold voltage distribution
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by performing encoding of data to be programmed into a target wordline based on the program state of adjacent wordlines before actually programming the data. This advance preparation allows the system to anticipate and compensate for wordline interference effects, adjusting the data conditions in advance to maintain reliable threshold voltage distributions even as memory integration increases

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements local quality by applying different encoding conditions to different portions of data based on the local program state of adjacent memory cells. Specifically, first portion of data adjacent to first portion of memory cells in first state satisfies first condition, while second portion of data adjacent to second portion of memory cells in second state satisfies second condition. This localized approach allows precise compensation for wordline interference in each region, maintaining threshold voltage distribution reliability across the entire integrated memory structure

Inventive Principle:
Principle #3Local quality

2Productivity

If data is programmed into target wordline without considering adjacent wordline state, then the programming speed is improved, but the data reliability is degraded due to wordline interference

Engineering Contradiction:
Improveprogramming speedVSAvoiddata reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying the data conditions (voltage levels, programming pulses) based on the program state of adjacent wordlines. The storage controller adjusts encoding parameters dynamically - when adjacent wordlines are in different program states, different encoding conditions are applied to the target wordline data. This parameter adaptation compensates for wordline interference effects while maintaining efficient programming operations, thus preserving both speed and reliability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250014647A1Storage device and method of operating the same
Publication Date: 2025.01.09 SAMSUNG ELECTRONICS CO LTD
  • US20250014647A1 patent drawing
  • US20250014647A1 patent drawing
  • US20250014647A1 patent drawing

AI summary

A storage device includes a nonvolatile memory device including a plurality of first memory cells coupled to a first wordline and a plurality of second memory cells coupled to a second wordline, the first wordline and the second wordline being adjacent to each other, and a storage controller configured to control the nonvolatile memory device. The storage controller is further configured to encode data to be programmed into the plurality of second memory cells, based on a program state of each of the plurality of first memory cells, and encode the data to be programmed into the second wordline such that a first portion of the data to be written into a first portion of the plurality of second memory cells satisfies a first condition, and a second portion of the data to be written into a second portion of the plurality of second memory cells satisfies a second condition.