Storage Controller Encryption Cores for Read/Write Speed
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Solution Overview
Problem
The increasing write and read speeds of nonvolatile memory devices are hindered by the encryption or decryption processes, which act as a bottleneck, necessitating an improvement in encryption or decryption speed to maintain high operational speeds.
Innovation Solution
A storage device with a memory controller that includes multiple encryption and decryption cores, which perform initialization in parallel and sequentially select initial tweak values to enhance encryption or decryption efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption or decryption is performed using a single core sequentially, then security is maintained, but the operating speed of the storage device is hindered and becomes a bottleneck
Solution Approach 1:
The encryption/decryption function is segmented into multiple independent cores (first encryption core, second encryption core, etc.). Each core can independently process different data blocks in parallel, transforming the sequential single-core operation into multi-core parallel operation, thereby resolving the contradiction between security and speed.
Solution Approach 2:
Tweak values are generated in advance and stored in a lookup table before actual encryption/decryption operations. This preliminary generation of cryptographic parameters eliminates the need for time-consuming key derivation during data processing, significantly improving encryption speed while maintaining security through the use of stored tweak values.
2Productivity
If multiple encryption cores operate in parallel, then encryption speed is improved, but the complexity of managing multiple cores and their synchronization increases
Solution Approach 1:
Multiple encryption cores operate in a periodic, cyclic manner where each core processes a specific number of data blocks before passing control to the next core. This periodic operation pattern simplifies synchronization management compared to fully parallel operations, as cores take turns in a predictable sequence, reducing the complexity of coordinating multiple concurrent processes while maintaining high throughput.
Data Source
AI summary
Storage devices are provided which include a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory controller includes a plurality of encryption and decryption cores, the plurality of encryption and decryption cores perform initialization at the same time and generate a plurality of initial tweak values, sequentially select the plurality of initial tweak values to perform encryption or decryption, and perform the encryption or the decryption in parallel by using one or more initial tweak values selected from the plurality of initial tweak values.