Storage Controller Erasure Correction for Memory Reliability
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Solution Overview
Problem
Advanced memory technologies face challenges in managing increased bit error rates due to miniaturization and multi-level cell adoption, which affect performance, traffic, power consumption, and latency.
Innovation Solution
A controller and storage device system that employs a processing circuit to write and read data fragments across multiple memory chips, utilizing erasure correction codes and error correction codes to ensure high reliability and performance, with mechanisms for monitoring and notifying completion status via signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes such as LDPC codes and soft decision repetition codes are introduced to correct bit errors in advanced memory, then reliability is improved, but performance such as traffic between memory chips and controller, power consumption, and latency deteriorates
Solution Approach 1:
The data is divided into multiple data fragments and distributed across different memory chips. This segmentation allows the system to perform error correction on individual fragments independently, reducing the overall computational burden and improving performance while maintaining reliability through distributed error correction capabilities.
Solution Approach 2:
The system performs error correction only on the necessary number of data fragments to achieve the required reliability level, rather than correcting all fragments uniformly. This partial action approach reduces unnecessary computational overhead, lowering power consumption and latency while maintaining adequate error correction capability.
2Reliability
If error correction codes are applied to all data fragments, then reliability is improved, but power consumption increases
Solution Approach 1:
The system selectively applies error correction to only the necessary data fragments based on the required reliability level, avoiding unnecessary power consumption from correcting all fragments. This partial correction approach maintains adequate reliability while significantly reducing power usage.
Solution Approach 2:
The system dynamically adjusts the error correction parameters and intensity based on the specific data fragment characteristics and required reliability levels, optimizing power consumption by applying stronger correction only where necessary and weaker or no correction where sufficient margins exist.
3Reliability
If error correction is performed on all memory chips before reading data, then reliability is improved, but latency increases
Solution Approach 1:
Error correction is performed on data fragments in advance during the write operation or in parallel preparation stages, so that when read operations occur, the correction work has already been completed. This preliminary action eliminates latency during actual data retrieval while maintaining reliability through pre-applied error correction.
Solution Approach 2:
The system performs error correction on only the necessary number of data fragments rather than all fragments, reducing the total time required for correction operations. This partial correction approach maintains adequate reliability while minimizing the latency impact of error correction processing.
4Quantity of substance
If data is distributed across multiple memory chips, then capacity is improved, but device complexity increases
Solution Approach 1:
Data is divided into standardized fragments with consistent formatting and metadata structures, making the distributed storage system manageable through uniform processing rules. This segmentation approach increases capacity through parallel storage while controlling complexity through standardized fragment handling procedures.
Solution Approach 2:
The controller is designed with universal processing capabilities that can handle any data fragment from any memory chip using the same error correction and data retrieval algorithms. This multi-functionality allows the system to scale capacity by adding more chips without proportionally increasing operational complexity, as the same universal procedures manage all fragments regardless of source.
Data Source
AI summary
A controller includes a processing circuit that writes each of a plurality of data fragments each including a part of data to be written in one memory chip of a plurality of memory chips each having an error correction function, and reads the data fragments corresponding to the data to be read from the memory chips, a first encoder that encodes the data to be written with an erasure correction code such that each of the data fragments includes a parity, and a first decoder that performs erasure correction by use of a part of the data fragments corresponding to the data to be read according to a completion status or success or failure of error correction on a corresponding part of the data fragments in each of the memory chips, the completion status or the success or failure of the error correction being acquired via a signal line.