Storage Controller Early Termination Error Correction Latency

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Solution Overview

Problem

Storage devices face increased latency in read operations due to frequent uncorrectable errors, which existing technologies struggle to efficiently address.

Innovation Solution

A storage device with a controller that executes first error correction decoding on memory cells when a read operation fails, and determines whether to perform second error correction decoding based on an early termination flag and condition, thereby reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If second error correction decoding is always executed when first error correction decoding fails, then reliability is improved, but latency increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidread operation latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by selectively executing the second error correction decoding only when necessary (when early termination conditions are not met), rather than always executing it. This reduces unnecessary processing time while maintaining reliability for cases that actually need the additional decoding pass.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the parameter of decoding execution by introducing early termination flags and conditions that dynamically control whether the second error correction decoding is performed. This parameter-based control allows the system to adapt between executing full error correction (for reliability) or skipping to faster paths (for low latency) based on real-time decoding state.

Inventive Principle:

Principle #35Parameter changes

2Speed

If early termination is implemented to reduce latency, then read operation speed is improved, but error correction reliability may deteriorate

Engineering Contradiction:

Improveread operation speedVSAvoiderror correction accuracy

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent implements feedback mechanisms through early termination flags and conditions that monitor the decoding process. The system continuously evaluates decoding progress and only terminates early when confidence thresholds are met, ensuring reliability is maintained while enabling speed improvements when appropriate.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent introduces dynamic control of the error correction process through early termination flags that can be set or reset based on decoding conditions. This dynamic approach allows the system to adapt between aggressive early termination (for speed) and conservative full decoding (for reliability) based on real-time feedback from the decoding process.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12204405B2Storage device determining quickly whether error correction decoding has failed and method of operating the storage device

Publication Date: 2025.01.21 SK HYNIX INC

AI summary

A storage device may execute first error correction decoding on a plurality of memory cells when a read operation on the plurality of memory cells fails, and determine, when the first error correction decoding fails, whether to execute second error correction decoding on the plurality of memory cells based on at least one of a value of an early termination flag and whether an early termination condition is satisfied.