Storage Controller Hotness Determination for Mixed Bit-Density Memory
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Solution Overview
Problem
Existing storage devices face challenges in efficiently adapting to changing workload patterns and accurately distinguishing hot and cold data, leading to suboptimal performance and lifespan due to the use of memory regions with different bit-densities.
Innovation Solution
A controller is implemented that includes a CPU, a hotness determining circuit, a pattern detection circuit, and a parameter adjustment circuit to assess the hotness of logical addresses based on their frequency and recency, adjusting weights and storing data in memory regions with different bit-densities accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a storage device uses memory regions with different bit-densities to store data, then storage capacity is improved, but the ability to accurately distinguish hot and cold data deteriorates
Solution Approach 1:
The storage device divides memory regions into different bit-density segments (e.g., SLC, MLC, TLC, QLC) and applies different weight factors to logical addresses based on their hotness levels. This segmentation allows the system to store more data while maintaining accurate hot/cold data distinction through differentiated weight assignments for each memory region type.
Solution Approach 2:
Different weight factors are assigned to logical addresses depending on which memory region they map to. Hot data logical addresses receive higher weight factors when mapped to lower bit-density regions (like SLC), while cold data logical addresses receive lower weight factors when mapped to higher bit-density regions (like QLC). This local differentiation maintains measurement precision across diverse storage capacities.
2Device complexity
If the storage device uses a simple hotness determination method, then device complexity is reduced, but adaptability to changing workload patterns deteriorates
Solution Approach 1:
The weight factor for each logical address is dynamically adjusted based on its access pattern and hotness level. The system continuously monitors workload patterns and modifies weight factors in real-time, allowing the storage device to adapt to changing access patterns without requiring a complete redesign of the hotness determination mechanism.
Solution Approach 2:
The system implements a feedback loop where access patterns are monitored, hotness is determined based on accumulated weights, and weight factors are adjusted accordingly. This feedback mechanism enables the storage device to adapt to changing workload patterns while maintaining a relatively simple underlying weight accumulation structure.
3Productivity
If the storage device accurately determines hotness of logical addresses, then data classification performance is improved, but the time required for hotness calculation increases
Solution Approach 1:
The system calculates weights for logical addresses partially, focusing computation on recently accessed addresses and those with higher access frequencies. Instead of uniformly processing all logical addresses, the system applies excessive weighting to hot data candidates while using decay factors to reduce computation for cold data, thereby improving classification performance while reducing overall calculation time.
Solution Approach 2:
The system changes parameters such as weight factors and decay rates dynamically based on workload characteristics. By adjusting these parameters, the system can optimize the balance between classification accuracy and calculation speed, using heavier weighting for high-priority hotness determination scenarios and lighter weighting when speed is paramount.
Data Source
AI summary
A controller includes a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into a logical address list; a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address; and a parameter adjustment circuit decreasing a magnitude of the decay factor based on the repeatability index of the received logical addresses included in the logical address list, wherein the CPU is configured to control the memory device to store the data in one of the memory regions based on the hotness.