Storage Controller Interface Unit DMA Bandwidth Optimization
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Solution Overview
Problem
In multinode storage systems using RoCE over Ethernet, dual write operations lead to bandwidth compression between the processor, memory, and communication interface due to repeated access during data transfer, affecting storage system performance.
Innovation Solution
The storage system is configured with multiple storage controllers connected via Ethernet, where a dual write parameter is processed to generate requests for multiple storage controllers, storing these requests in queues and transferring data efficiently, reducing the need for repeated DMA access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual write is performed by storing WQE in SQ for each destination controller and executing DMA access twice, then data duplication between storage controllers is achieved, but bandwidth between processor-memory and interface is compressed
Solution Approach 1:
The patent merges multiple DMA access operations into a single access by combining the data transfer path. Instead of accessing memory separately for each destination controller, the system performs a single DMA access that simultaneously prepares data for multiple destinations, thereby reducing bandwidth consumption while maintaining data duplication functionality.
Solution Approach 2:
The patent implements preliminary action by pre-processing data in the interface unit's memory before DMA transfer. The interface unit stores incoming data in its internal memory first, then generates multiple WQE requests that reference this pre-stored data. This allows subsequent DMA operations to reference the same data buffer without re-reading from the source controller's memory, reducing repeated access overhead.
2Productivity
If dual write is performed with separate DMA access for each destination, then data is written to multiple controllers, but storage system performance is affected due to bandwidth compression
Solution Approach 1:
The patent segments the dual write operation into two distinct phases: (1) data reception and storage in the interface unit's memory, and (2) generation of multiple WQE requests that reference the stored data. This segmentation allows the data transfer and request generation to be decoupled, enabling parallel processing and reducing the critical path delay that would otherwise serialize multiple DMA accesses.
Solution Approach 2:
The interface unit acts as an intermediary between the source controller and multiple destination controllers. It receives data from the source, stores it in its internal memory, and then generates WQE requests that enable destinations to retrieve the data. This intermediary role eliminates the need for the source controller to directly manage multiple DMA accesses, reducing its processing burden and bandwidth consumption.
Data Source
AI summary
Each storage controller comprises a first storage unit, an interface unit, and a processing unit which sends, to the interface unit, a parameter which instructs n-fold write of writing data in each of n-number of (n is a natural number of 2 or more) other storage controllers. When the interface unit receives the parameter, the interface unit executes each processing of acquiring the data from the first storage unit and storing the data in the second storage unit, generating n-number of requests of writing the data in each of n-number of the other storage controllers, storing each of the generated requests in n-number of the queues corresponding to each of n-number of the other storage controllers, and processing each request stored in each queue and transferring the data stored in the second storage unit to each of n-number of the other storage controllers.