Storage Controller Interrupt Delay Optimization

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Solution Overview

Problem

In data storage systems, frequent interrupt requests from devices to hosts lead to inefficient CPU usage due to prolonged overhead periods, while polling methods are not always effective, resulting in suboptimal event handling.

Innovation Solution

A data storage device with a controller and non-volatile memory dynamically adjusts the timing of interrupt requests based on the CPU's status, using a buffer to store an interrupt delay value that is adjusted according to the CPU's idle or busy state, thereby reducing the frequency of interrupt requests and optimizing CPU utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the device frequently sends interrupt requests to the host, then event notification reliability is improved, but CPU efficiency deteriorates due to redundant overhead periods

Engineering Contradiction:

Improveevent notification reliabilityVSAvoidCPU efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamics by making the interrupt delay parameter adjustable and adaptive. The controller dynamically modifies the interrupt delay based on CPU status feedback, transitioning from a static fixed delay to a dynamic variable delay that responds to system conditions, thereby resolving the contradiction between reliable event notification and CPU efficiency

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by having the host send status information about CPU activity to the device, which then uses this feedback to adjust the interrupt delay. This closed-loop mechanism allows the system to learn from CPU behavior patterns and optimize interrupt timing, balancing reliability and efficiency

Inventive Principle:

Principle #23Feedback

2Measurement precision

If the CPU enters overhead period for each interrupt request, then event processing accuracy is improved, but time consumption increases due to repeated overhead periods

Engineering Contradiction:

Improveevent processing accuracyVSAvoidtime consumption

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by having the device accumulate multiple events in a buffer before triggering an interrupt. This allows the CPU to process multiple events in a single overhead period, reducing the frequency of context switching while maintaining processing accuracy, thus decreasing time consumption

Inventive Principle:

Principle #10Preliminary action

3Productivity

If the device waits for CPU availability before sending interrupt, then CPU resource occupation is reduced, but event response time increases

Engineering Contradiction:

ImproveCPU resource utilizationVSAvoidevent response time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies partial action by implementing a partial delay strategy where the interrupt is delayed only partially based on CPU status rather than completely blocked. The controller adjusts the delay duration dynamically, allowing some events to be processed quickly while avoiding excessive delays that would waste CPU resources, thus balancing response time and resource utilization

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS10896003B2Data storage device and system with interruption optimization

Publication Date: 2021.01.19 SHANNON SYST

AI summary

A data storage device with interruption optimization having a non-volatile memory and a controller is shown. The controller operates the non-volatile memory in response to a host. The controller has a buffer which is filled with an interrupt delay that is evaluated by the host according to the status of the central processing unit of the host. The controller delays sending an interrupt request to the host according to the interrupt delay.