Storage Controller Local Memory Segmentation for Overhead Reduction

The patent divides control information into two parts: frequently accessed control information is cached in local memory for each processor, while less frequently accessed control information remains in shared memory. This segmentation allows processors to access critical control data locally without incurring shared memory overhead, while still maintaining the ability to update shared memory when necessary to preserve cache coherence and hit rates.

The patent pre-loads control information from shared memory into local memory caches before it is needed for processing. By anticipating future access patterns and loading control data in advance, the system reduces the frequency of shared memory accesses during actual data processing operations, thereby reducing overhead while maintaining cache hit rates.

The patent implements a two-level caching structure where data is cached locally in each processor's memory and also maintained in shared memory. This segmentation allows processors to access frequently used data locally at high speed while reducing the frequency of shared memory accesses, thereby maintaining access speed benefits while reducing overhead.

The patent optimizes the caching strategy by identifying and caching locally the specific control information and data that each processor accesses most frequently. By tailoring the cache contents to local processor needs rather than uniformly caching all data, the system maximizes access speed for each processor while minimizing the total overhead of maintaining cache coherence in shared memory.