Storage Controller LRU Cache Retention with Application Time Hints

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Solution Overview

Problem

Conventional LRU cache replacement policies in storage controllers do not effectively incorporate application-specific maximum retention times, leading to inefficient cache management and potential data loss due to unnecessary retention of tracks beyond their useful lifespan.

Innovation Solution

Integrate application-indicated maximum retention times into LRU-based cache replacement mechanisms by generating multiple insertion points in the LRU list, adjusting insertion points based on retention times, and incorporating hints from applications to manage cache space more efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional LRU cache replacement policies are used without application-specific retention times, then cache management is simple, but tracks are retained beyond their useful lifespan leading to inefficient cache utilization

Engineering Contradiction:
Improvecache utilization efficiencyVSAvoidcache replacement mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The LRU list is segmented into multiple insertion points based on different retention time ranges. Each insertion point corresponds to a specific time window, allowing tracks to be placed at appropriate positions according to their application-indicated retention requirements rather than using a single uniform LRU list

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cache replacement mechanism dynamically adjusts insertion points based on application-specific retention time indications. The system adapts the LRU list structure by creating multiple insertion points that move and adjust according to the retention time requirements of different tracks, making the replacement policy flexible and application-aware

Inventive Principle:
Principle #15Dynamics

2Reliability

If multiple insertion points are generated in the LRU list based on retention times, then tracks are retained for optimal duration, but the cache management complexity increases

Engineering Contradiction:
Improvedata retention accuracyVSAvoidLRU list structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LRU list is divided into multiple segments or insertion points, where each insertion point corresponds to a specific retention time range. This segmentation allows tracks to be placed at the appropriate insertion point based on their application-indicated retention time, ensuring they are retained for the optimal duration without requiring complex external management mechanisms

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the parameter of the LRU list from a single linear structure to multiple insertion points with different time characteristics. By adjusting the insertion points based on retention time parameters provided by applications, the system achieves accurate data retention control while maintaining a structured approach to cache management

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12399838B2Integration of application indicated maximum time to cache to least recently used track demoting schemes in a cache management system of a storage controller
Publication Date: 2025.08.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12399838B2 patent drawing
  • US12399838B2 patent drawing
  • US12399838B2 patent drawing

AI summary

A computational device receives an indication that specifies a maximum retention time in cache for a first plurality of tracks, wherein no maximum retention time is specified for a second plurality of tracks. A plurality of insertions points are generated in a least recently used (LRU) list, wherein different insertion points in the LRU list correspond to different amounts of time that a track of the first plurality of tracks is expected to be retained in the cache, wherein the LRU list is configured to demote both tracks of the first plurality of tracks and the second plurality of tracks from the cache.