Storage Controller Map Recovery via Error Detection
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Solution Overview
Problem
Storage systems face challenges in efficiently managing and recovering logical-to-physical address maps due to limited volatile memory capacity, leading to errors when transferring data from unreliable host memory buffers to non-volatile memory.
Innovation Solution
A controller in the storage system receives a logical-to-physical map from volatile memory, checks for errors using error detection codes, and attempts to recover corrupted entries by checking recent transaction logs and open blocks in non-volatile memory before storing the map, ensuring accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the logical-to-physical address map is stored in volatile memory for faster access, then access speed is improved, but data reliability deteriorates due to volatility and limited capacity causing data loss
Solution Approach 1:
The patent implements error detection codes (such as CRC) when writing data to volatile memory before potential corruption occurs. This preliminary error detection mechanism allows the system to identify and handle corrupted data before it causes failures, thus maintaining both fast access speeds and data reliability.
Solution Approach 2:
The patent introduces an intermediary error detection and recovery mechanism that sits between the volatile memory and the system operations. This intermediary layer detects errors in volatile memory data and retrieves correct data from non-volatile memory or host buffer, thus protecting against volatility while maintaining fast access paths.
2Reliability
If error detection codes are implemented to verify data integrity, then data reliability is improved, but processing time increases
Solution Approach 1:
The patent applies error detection selectively - error detection codes are implemented at critical boundaries (when data is written to volatile memory and when it is read back) rather than continuously during all operations. This partial application maintains data integrity while minimizing the time overhead of error checking.
Solution Approach 2:
The system uses error detection codes with efficient algorithms (such as CRC) that can be computed quickly, allowing the system to rush through the verification process with minimal delay. The error detection is performed in a streamlined manner that does not significantly impact overall processing throughput.
3Speed
If the entire logical-to-physical address map is stored in volatile memory, then access speed is improved, but memory capacity requirements increase
Solution Approach 1:
The patent segments the logical-to-physical address map into multiple portions or chunks. Only the actively needed portions are loaded into volatile memory at any given time, while other portions remain in non-volatile memory or host buffer. This segmentation allows fast access to current data while reducing the total volatile memory capacity required.
Solution Approach 2:
The system dynamically manages the contents of volatile memory, loading and unloading portions of the address map based on current access patterns and needs. This dynamic allocation ensures that volatile memory is used efficiently for high-speed access to active data while inactive data resides in lower-speed storage, optimizing both speed and capacity utilization.
Data Source
AI summary
A storage system and method for recovering data corrupted in a host memory buffer are provided. In one embodiment, a storage system is provided comprising a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to receive a logical-to-physical map from a volatile memory of a host for storage in the storage system's non-volatile memory; determine if there is an error in an entry in the logical-to-physical map; in response to determining that there is no error in the logical-to-physical map, store the logical-to-physical map in the non-volatile memory; and in response to determining that there is an error in an entry in the logical-to-physical map, attempt to recover the entry from a location in the storage system before storing the logical-to-physical map in the non-volatile memory. Other embodiments are provided.