Storage Controller Memory Mapping for Data Transfer Efficiency
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Solution Overview
Problem
The existing storage system faces challenges in improving response performance from the host's perspective due to difficulties in rapid data transfer between storage apparatuses, leading to inefficiencies in write processing.
Innovation Solution
A storage system with bidirectionally communicable storage controllers, each equipped with a front-end unit for protocol control, an interface unit for inter-controller communication, and subdivided memory areas, allowing direct data packet transfer without intermediate buffers, enabling efficient command processing and data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write data is stored temporarily in memory in the first storage apparatus before transfer, then data redundancy is achieved, but data transfer speed and response performance deteriorate
Solution Approach 1:
The patent extracts the temporary storage function from the first storage apparatus's main memory by introducing a dedicated buffer memory in the second storage apparatus. This separates the data reception function (first storage apparatus) from the temporary storage function (buffer memory in second storage apparatus), enabling direct data transfer without holding data in the first apparatus's memory, thus resolving the contradiction between redundancy and transfer speed.
2Reliability
If data is transferred via intermediate storage in the second storage apparatus, then data redundancy is improved, but response performance from host perspective deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-configuring the buffer memory in the second storage apparatus with mapping information and preparation data before actual data transfer occurs. The buffer memory is ready to receive and store data immediately when transferred from the first storage apparatus, eliminating intermediate processing delays and improving overall response time while maintaining redundancy.
3Productivity
If memory areas are not subdivided and mapped between controllers, then device complexity is reduced, but data transfer efficiency and memory utilization deteriorate
Solution Approach 1:
The patent segments the buffer memory in the second storage apparatus into multiple buffer areas, each mapped to corresponding memory areas in the first storage apparatus. This segmentation enables parallel data transfer operations and improves memory utilization efficiency. The mapping relationships are managed through data structure information stored in the buffer memory, which organizes the segmented areas systematically, making the complexity manageable while achieving high transfer efficiency.
Data Source
AI summary
A processor of a storage controller stores a parameter according to a command that has been transferred from a front-end unit to a first area in a first memory area and issues notification to the front-end unit regarding an address of a second area in a second memory area which is mapped to the first area, the front-end unit generates a data packet whose destination is the notified address and stores the generated data packet at the address of the second memory area, and an interface unit reads the parameter stored in the first area in the first memory area which is mapped to the second area of the address based on the destination address stored in a header of the data packet which has been stored in the second memory area and executes processing of the system function according to the command.