Storage Controller Spare-Space Memory Operations for CPU Offload
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Solution Overview
Problem
Existing memory operations in storage systems waste CPU resources due to high processing loads during bulk data copy/move operations, as they do not effectively utilize the spare space within storage controllers.
Innovation Solution
Utilize the spare space within the storage controller's spare engine to perform memory operations, such as memory initialization, copy, and move, by allocating registers to handle these tasks, reducing CPU intervention and optimizing memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU performs bulk data copy/move operations, then the memory operations are completed, but the CPU processing load increases and resources are wasted
Solution Approach 1:
The patent extracts the memory operation execution task from the CPU and transfers it to the storage controller's spare engine. The CPU only initiates the operation by configuring the spare space with source/destination addresses and operation parameters, while the actual data copying/moving is performed autonomously by the spare engine using allocated registers, thereby reducing CPU processing load and resource consumption.
Solution Approach 2:
The spare engine within the storage controller performs memory operations autonomously without continuous CPU intervention. Once the CPU configures the spare space with necessary parameters (source address, destination address, operation type), the spare engine self-manages the entire data copy/move process using its own registers and control logic, making the system self-sufficient for these operations.
2Ease of operation
If the CPU handles simple memory read/write operations, then the data is transferred, but essential CPU resources are wasted that could be used for complex operations
Solution Approach 1:
The patent extracts simple memory read/write operations from the CPU's responsibility and assigns them to the storage controller's spare engine. The CPU only performs high-level configuration (setting addresses and operation parameters in the spare space), while the actual data access operations are executed independently by the spare engine, freeing CPU resources for complex computational tasks.
Solution Approach 2:
The spare engine is designed to handle multiple types of memory operations (read, write, copy, move) through a unified interface. By configuring the spare space with appropriate parameters, the same hardware resource can perform various memory operations that would traditionally require different CPU intervention levels, demonstrating multi-functionality at the storage controller level.
Data Source
AI summary
A method performed by a host device to perform memory operations improving memory operations comprises receiving a request to perform at least one memory operation on a storage device. The method further includes determining a current processing load of a processing unit of the host device upon receiving the request to perform the at least one memory operation. The method further includes transmitting a configuration request to the storage device to configure a spare space within a storage controller of the storage device in response to determining that the current processing load exceeds a load threshold value. The configuring of the spare space includes allocating a plurality of registers within the spare space to perform the at least one memory operation on the storage device.