Storage Controller Memory Area Segmentation for Predictable Latency
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Solution Overview
Problem
Current storage devices with nonvolatile memory struggle to guarantee predictable latency in input/output operations, particularly in solid state drives (SSDs), due to the limitations of existing technologies in managing memory areas and processing requests efficiently.
Innovation Solution
The implementation of a storage device with a controller that logically divides memory into sets, distributing them into high, normal, and low priority groups, and dynamically manages resources and operation periods to ensure predictable latency by transitioning between deterministic and non-deterministic windows for read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory areas are managed without priority grouping, then device complexity is reduced, but input/output determinism and predictable latency cannot be guaranteed
Solution Approach 1:
The memory area is segmented into multiple priority groups (first priority group, second priority group, third priority group) to enable differentiated handling of read and write requests. This segmentation allows the system to guarantee predictable latency for high-priority operations while managing overall memory complexity through structured organization.
Solution Approach 2:
The controller dynamically transitions between deterministic window mode and non-deterministic window mode based on operational requirements. In deterministic window mode, the system guarantees predictable latency by processing requests from specific priority groups, while in non-deterministic window mode, it performs background tasks like garbage collection, providing adaptive memory management.
2Reliability
If deterministic window mode is used for all operations, then predictable latency is guaranteed, but productivity decreases due to limited operational flexibility
Solution Approach 1:
The controller alternates between deterministic window mode and non-deterministic window mode in periodic cycles. During deterministic windows, it processes high-priority requests with guaranteed latency, while during non-deterministic windows, it performs background maintenance tasks. This periodic switching ensures both predictable latency for user operations and system productivity through efficient background task execution.
3Device complexity
If all memory areas are treated equally, then device complexity is minimized, but resource allocation efficiency deteriorates under varying workload conditions
Solution Approach 1:
Different priority groups are assigned different quality levels of service. The first priority group receives guaranteed latency treatment with dedicated processing resources, while other groups receive standard service. This local differentiation of quality allows efficient resource allocation under varying workload conditions without requiring complex global control logic.
Data Source
AI summary
According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller manages memory area sets. The controller distributes a first memory area set into a first group. The controller distributes a second memory area set into a second group. The controller comprises first to fourth circuits. The first circuit processes a first read request from a host to the first memory area set. The second circuit processes a first write request from the host to the first memory area set. The third circuit processes a second read request from the host to the second memory area set. The fourth circuit processes a second write request from the host to the second memory area set.