Storage Controller Multi-Core Rearrangement for Out-of-Sequence Writes
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Solution Overview
Problem
Conventional flash memory controllers can only support a queue depth of one and are unable to simultaneously write to multiple zones, leading to longer response times for large data amounts due to their inability to handle out-of-sequence write command signals.
Innovation Solution
A storage device controller with multiple processor cores and an interface circuit that receives and rearranges out-of-sequence write address information to ensure sequential writing across multiple zones, supporting the NVMe zoned namespaces interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional flash memory controller supports only queue depth of one, then the device structure remains simple, but the response time increases for large data amounts and multiple zones cannot be simultaneously written
Solution Approach 1:
The controller is divided into multiple processor cores (first processor core, second processor core, etc.) that can independently handle different write commands. Each core processes a portion of the write operations simultaneously, enabling parallel processing of multiple zones and improving write throughput while maintaining manageable complexity through modular architecture
Solution Approach 2:
The patent transitions from single-dimensional sequential processing to multi-dimensional parallel processing by introducing multiple processor cores that operate simultaneously on different write commands. This dimensional expansion allows the controller to handle out-of-sequence write commands across multiple zones in parallel, dramatically improving productivity
2Loss of time
If the controller processes write commands sequentially, then the processing logic remains simple, but the response time becomes longer for large data amounts
Solution Approach 1:
The controller receives and buffers multiple write commands before execution, allowing commands to be prepared and organized in advance. The buffer stores incoming write commands with their associated metadata (zone information, LBA ranges), enabling the processor cores to efficiently retrieve and execute them in parallel without waiting for sequential processing to complete
Solution Approach 2:
The patent changes the processing parameter from single-thread sequential execution to multi-thread parallel execution. By introducing multiple processor cores that can independently execute write commands simultaneously, the system transforms the time complexity of processing large data amounts, reducing response time while the parameter change in processing architecture manages the complexity
3Productivity
If the controller supports only sequential writing in a single zone, then the writing process remains simple, but multiple zones cannot be simultaneously written
Solution Approach 1:
The storage device is divided into multiple zones that can be independently managed and written to simultaneously. Each processor core can handle write operations to different zones in parallel, and the controller maintains separate tracking of zone boundaries, LBA ranges, and write pointers for each zone, enabling simultaneous multi-zone writing while managing complexity through segmented zone management
Solution Approach 2:
The processor cores are designed with universal functionality to handle write operations across any zone. Each core can process write commands for any zone by interpreting the zone identifier and LBA range in the command, making the processing mechanism multi-functional rather than dedicated to specific zones. This universality enables simultaneous writing to multiple zones while avoiding the complexity of dedicated hardware for each zone
Data Source
AI summary
A method of a storage device controller includes: using an interface circuit for receiving and storing different write address information of different write command signals sent from a host device, the different write address information being out of sequence; and, using multiple processor cores to rearrange the different write address information in sequence and then write data into at least one storage zone according to the different write address information rearranged in sequence.