Storage Controller Overlay Code Loading With Limited Buffer Memory
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Solution Overview
Problem
Insufficient buffer area in storage devices leads to difficulties in loading firmware, impacting operating efficiency.
Innovation Solution
Efficient use of buffer areas by allocating logical memory addresses in advance for overlay codes and connecting them to buffer areas, while using unoccupied addresses for frequently used non-overlay codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the controller loads firmware into buffer areas for execution, then the operation efficiency of firmware is improved, but the buffer area may be insufficient to accommodate all required codes
Solution Approach 1:
The patent segments the buffer memory into multiple buffer areas, each capable of storing different codes. This segmentation allows the controller to load only the necessary portions of firmware into available buffer spaces, optimizing the use of limited buffer resources while maintaining efficient firmware operation.
Solution Approach 2:
The controller allocates logical memory addresses to buffer areas in advance, before actually loading the codes. This preliminary allocation ensures that when codes need to be loaded, suitable buffer spaces are already prepared and designated, enabling efficient loading operations without contention or delays.
2Adaptability or versatility
If the controller allocates buffer areas for overlay codes, then more code types can be loaded, but the buffer management complexity increases
Solution Approach 1:
The patent creates a universal buffer management mechanism where buffer areas can be dynamically allocated to different types of codes (overlay or non-overlay) based on need. The same buffer management logic handles both code types, providing versatility in code loading while avoiding the need for separate specialized management systems for each code type.
Solution Approach 2:
The buffer area allocations are dynamic rather than static. The controller can adjust which buffer areas are connected to which logical memory addresses based on the specific loading requirements. This dynamic allocation allows the system to adapt to different code loading scenarios without increasing structural complexity.
3Productivity
If the controller connects logical memory addresses to buffer areas dynamically, then buffer usage efficiency is improved, but the addressing complexity increases
Solution Approach 1:
The patent introduces a mapping mechanism that acts as an intermediary between logical memory addresses and physical buffer areas. This mapping layer handles the complexity of dynamic connections, allowing the controller to efficiently manage buffer usage while abstracting the addressing complexity away from the main firmware execution path.
Data Source
AI summary
Data storage devices and controllers are disclosed. In an embodiment of the disclosed technology, an occupied logical memory address for loading an overlay code stored in a memory into a buffer memory is allocated and set in advance, and the loading of the overlay code is performed using the occupied logical memory address. Therefore, the overlay code can be loaded without allocating in advance a buffer area of the buffer memory, and thus the buffer memory may be efficiently used and the loading of the overlay code may be effectively performed.