Storage Controller P2P Transfer with Fine-Grained Cache Updates
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Solution Overview
Problem
Existing storage devices face increased data transmission overhead when multiple hosts access shared memory pools, necessitating peer-to-peer (P2P) data transfer without host intervention, and existing methods do not effectively manage cache coherence during such transfers.
Innovation Solution
A storage device with a non-volatile memory and a storage controller that includes a cache memory, interface circuit, buffer memory, address translation circuit, and cache controller, which manages mapping information to translate logical addresses to device physical addresses, enabling efficient P2P data transfer and cache updates in units smaller than block or page sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If storage devices transmit/receive data in peer-to-peer manner without host intervention, then data transmission overhead is reduced, but cache coherence management becomes more complex
Solution Approach 1:
The patent introduces an address translation circuit as an intermediary component that automatically manages address mapping between logical addresses and device physical addresses during P2P data transfer. This intermediary handles the complex cache coherence management tasks, allowing storage devices to perform efficient P2P transfers while the address translation circuit maintains cache consistency without requiring host intervention.
Solution Approach 2:
The storage device performs self-service by implementing an internal address translation mechanism that automatically manages cache coherence during P2P operations. The device independently translates logical addresses to device physical addresses and updates cache memories without external host control, enabling both high data transmission efficiency and automated cache management.
2Ease of manufacture
If cache updates are performed in block or page units, then data management is simplified, but unnecessary data transmission and energy consumption increase
Solution Approach 1:
The patent segments the cache update operation into finer granularity units by implementing address translation at the logical address level rather than block or page level. This allows the system to update only the specific cache lines that correspond to the actual data being transferred, rather than updating entire blocks or pages, thereby reducing unnecessary energy consumption while maintaining manageable complexity through the address translation circuit.
Solution Approach 2:
The patent changes the granularity parameter of cache updates from traditional block/page units to finer logical address-based units. By translating logical addresses to device physical addresses, the system can precisely control which cache areas are updated, reducing the amount of data transmission and energy consumption while the address translation mechanism keeps the management process tractable.
3Reliability
If host intervention is used to transmit data between storage devices, then cache coherence can be managed, but data transmission overhead increases
Solution Approach 1:
The patent extracts the cache coherence management function from the host and relocates it to the storage device itself, specifically to the address translation circuit. This extraction allows P2P data transfer to occur without host intervention, reducing data transmission overhead, while the address translation circuit independently maintains cache coherence, ensuring reliability is preserved.
Solution Approach 2:
The storage device performs self-service by implementing autonomous cache coherence management through its address translation circuit. The device independently handles address translation and cache updates during P2P operations without requiring host involvement, thereby eliminating host-related transmission overhead while maintaining proper cache coherence through internal self-management mechanisms.
Data Source
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AI summary
A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.