Storage Controller Load Balancing via Packet Format Routing
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Solution Overview
Problem
Computational storage devices face challenges in efficiently managing resource consumption and latency in processing large data tasks, as existing solutions do not effectively distribute workload without imposing overhead on processors.
Innovation Solution
A storage device architecture that includes a nonvolatile memory device, buffer memory, and a storage controller, which accesses the nonvolatile memory only for specific packet formats and the buffer memory for others, allowing for load balancing between computational storage devices without processor intervention through a root complex.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If computational storage devices process tasks delegated from processors, then processor resource consumption is reduced, but device complexity and task distribution management become more challenging
Solution Approach 1:
The patent introduces a root complex as an intermediary component between processors and computational storage devices. The root complex manages task distribution and load balancing, absorbing the complexity of coordination away from both processors and storage devices. This mediator handles packet routing, device selection, and workload allocation, thereby reducing processor resource consumption while avoiding direct complexity at the storage device level.
Solution Approach 2:
The system segments task management functions across multiple components: processors generate tasks, the root complex manages distribution and load balancing, and computational storage devices execute tasks. This segmentation allows each component to focus on specific functions, reducing overall system complexity while enabling efficient resource utilization and load distribution.
2Productivity
If multiple computational storage devices are used for load balancing, then processing capacity increases, but coordination overhead and system complexity increase
Solution Approach 1:
The root complex serves as a central coordinator that manages multiple computational storage devices. It receives tasks from processors, monitors device utilization, and distributes tasks appropriately. This intermediary approach enables load balancing across multiple devices to increase processing capacity while the root complex absorbs the coordination overhead, preventing complexity from propagating to individual storage devices.
Solution Approach 2:
The system implements feedback mechanisms where computational storage devices report their utilization status to the root complex. The root complex uses this feedback information to dynamically adjust task distribution, balancing load across devices. This feedback loop enables efficient utilization of multiple devices for increased productivity while maintaining manageable coordination through automated load balancing decisions.
3Measurement precision
If processors directly manage task distribution to storage devices, then control precision is high, but processor latency increases
Solution Approach 1:
The patent extracts the task distribution and load balancing functions from processors and places them in the root complex. This extraction removes the time-consuming coordination operations from the processor's critical path, reducing processor latency. The root complex handles the complex task of selecting appropriate storage devices and routing tasks, while processors simply issue tasks and receive results, significantly reducing their involvement time.
Solution Approach 2:
The root complex acts as an intermediary that handles task routing and device selection between processors and storage devices. This mediator absorbs the coordination overhead and latency associated with task distribution, allowing processors to operate with lower latency. The root complex maintains precise control over task distribution to appropriate devices while preventing this control complexity from increasing processor latency.
Data Source
AI summary
Disclosed is a storage device which includes a nonvolatile memory device, a buffer memory, a port that is connected with an external device, and a storage controller. When a command received from the external device through the port corresponds to a first packet format, the storage controller accesses the nonvolatile memory device by using the buffer memory in response to the command. When the command received from the external device through the port corresponds to a second packet format, the storage controller accesses the buffer memory without accessing the nonvolatile memory device in response to the command.