Storage Controller Parity Management for Memory Endurance
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Solution Overview
Problem
As memory cells in storage devices are miniaturized and their endurance decreases, there is a need for improving error correction capability to reuse reliability-reduced memory cells by expanding the parity area where parity bits are stored.
Innovation Solution
A storage controller method that determines the program/erase count of target pages, identifies sectors of high and low reliability, and expands the parity area of low-reliability sectors by moving a margin region from high-reliability sectors, thereby enhancing error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the parity area size is increased to improve error correction capability, then the reliability of memory cells is improved, but the storage capacity is reduced
Solution Approach 1:
The patent applies local quality by dynamically adjusting the parity area size for different sectors based on their individual reliability characteristics. Sectors with higher P/E counts (lower reliability) are allocated larger parity areas, while sectors with lower P/E counts (higher reliability) are allocated smaller parity areas. This localized adaptation resolves the contradiction by optimizing error correction resources where needed without uniformly reducing storage capacity across all sectors.
Solution Approach 2:
The patent implements dynamics by making the parity area size adjustable and reconfigurable based on real-time reliability assessment. The system dynamically determines P/E counts for different sectors and adjusts parity area allocations accordingly, rather than using a fixed parity area size. This dynamic approach allows the system to adapt to changing reliability conditions and optimize the balance between error correction capability and storage capacity.
2Quantity of substance
If memory cells are miniaturized to increase storage density, then the storage capacity is improved, but the endurance and reliability of memory cells deteriorate
Solution Approach 1:
The patent applies parameter changes by monitoring and utilizing P/E count parameters to assess memory cell reliability. The system changes the parity area allocation parameter based on the assessed reliability, allowing miniaturized memory cells to be used effectively by compensating for their reduced endurance through adaptive error correction. This enables the system to maintain reliability while benefiting from the high storage density of miniaturized cells.
3Reliability
If the parity area is expanded for reliability-reduced memory cells, then the error correction capability is improved, but the available storage space is reduced
Solution Approach 1:
The patent resolves this contradiction by applying local quality through sector-specific parity area allocation. Instead of uniformly expanding the parity area for all reliability-reduced memory cells, the system identifies individual sectors with high P/E counts and selectively expands parity areas only for those sectors. This localized approach improves error correction capability where needed while minimizing the impact on available storage space.
Solution Approach 2:
The patent applies partial action by expanding parity areas only for the portions of storage (specific sectors) that require enhanced error correction, rather than expanding parity areas for the entire storage device. This partial approach allows the system to improve reliability for reliability-reduced memory cells without excessively reducing the overall available storage space.
Data Source
AI summary
An operating method of a storage controller which communicates with a non-volatile memory device is provided. The method includes determining whether a program/erase (P/E) count of a target page including a plurality of sectors is greater than or equal to a P/E threshold value; based on determining that the P/E count of the target page is greater than or equal to the P/E threshold value, fetching the target page; determining a first sector having high reliability and a second sector having low reliability from the plurality of sectors of the fetched target page; and expanding a second parity area of the second sector by moving a margin region in a first parity area of the first sector to the second parity area of the second sector.