Storage Controller Parity Reduction for Ungraceful Shutdown Data Protection

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Solution Overview

Problem

Data storage devices face data loss during ungraceful shutdowns due to the lack of power warning from the host, leading to incomplete write operations and data loss in volatile memory, which existing technologies fail to adequately address.

Innovation Solution

A data storage device equipped with a controller that detects ungraceful shutdowns and uses a reduced set of parity bits to store data in non-volatile memory, determining the number based on factors like non-volatile memory age, program-erase count, or power loss history, and later generates the full set of parity bits upon power-up to ensure data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a capacitor is used to provide power during ungraceful shutdown, then data loss is prevented, but device cost and complexity increase

Engineering Contradiction:

Improvedata loss preventionVSAvoidcapacitor size

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies partial action by using a reduced set of parity bits instead of the full set during ungraceful shutdowns. This allows the capacitor to provide power for a shorter duration since fewer bits need to be written, thereby reducing the required capacitor size while still achieving the goal of preventing data loss.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the parameter of parity bit quantity dynamically based on shutdown conditions. During ungraceful shutdowns, a reduced number of parity bits is used, while during graceful shutdowns, the full set of parity bits is generated. This parameter change allows the system to adapt power requirements to actual needs, reducing capacitor size.

Inventive Principle:

Principle #35Parameter changes

2Device complexity

If a reduced set of parity bits is used during ungraceful shutdown, then capacitor size is reduced, but data integrity protection is weakened

Engineering Contradiction:

Improvecapacitor sizeVSAvoiddata integrity

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent implements a dynamic parity bit generation strategy where the number of parity bits adjusts based on the shutdown condition. During ungraceful shutdowns, a reduced set is used to minimize power requirements. During normal operations and graceful shutdowns, the full set of parity bits is generated to provide complete data integrity protection. This dynamic approach balances reliability and device complexity.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent applies preliminary action by detecting the ungraceful shutdown condition and switching to reduced parity bit mode before the capacitor power is depleted. This allows the system to prioritize getting data to non-volatile memory with minimal power consumption, while still providing some level of protection.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If the full set of parity bits is generated during ungraceful shutdown, then data integrity is maximized, but the time available for writing data is exceeded

Engineering Contradiction:

Improvedata integrityVSAvoidpower duration

Core Design Contradiction:

ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent uses partial action by generating only a reduced set of parity bits during ungraceful shutdowns instead of the full set. This reduces the total number of bits that need to be written to non-volatile memory, thereby reducing the power duration required and ensuring data can be saved within the limited capacitor power window.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent applies preliminary anti-action by preemptively reducing the parity bit set size in anticipation of the limited power duration available during ungraceful shutdowns. This prevents the situation where full parity generation would exceed the available power window, ensuring data integrity is maintained within practical constraints.

Inventive Principle:

Principle #9Preliminary anti-action

4Reliability

If more parity bits are used, then error protection is improved, but the amount of data to be written increases

Engineering Contradiction:

Improveerror protectionVSAvoidwrite operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the parameter of parity bit quantity based on operational conditions. During ungraceful shutdowns, the number of parity bits is reduced to minimize write operation time and power consumption. During normal operations, the full set of parity bits is used to provide maximum error protection. This parameter adaptation resolves the contradiction between protection level and write time.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11797445B2Data storage device and method for preventing data loss during an ungraceful shutdown

Publication Date: 2023.10.24 WESTERN DIGITAL TECHNOLOGIES INC

AI summary

A data storage device and method for preventing data loss during an ungraceful shutdown are provided. In one embodiment, a data storage device is provided comprising a volatile memory; a non-volatile memory; and a controller. The controller is configured to detect an ungraceful shutdown; and in response to detecting the ungraceful shutdown: generate a reduced set of parity bits for data stored in the volatile memory, wherein the reduced set of parity bits comprises fewer parity bits than a full set of parity bits used in a graceful shutdown; and store the data and the reduced set of parity bits in the non-volatile memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.