Storage Controller Parity Data Management via Zonal RAM Segmentation

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Solution Overview

Problem

Storage devices, such as SSDs, face limitations due to the high demand for RAM space for generating and storing parity data, leading to increased costs and reduced capabilities, as well as slower data transfer speeds that cause bottlenecks during writing operations.

Innovation Solution

Implementing a method where a storage device with a controller and two types of RAM (DRAM and SRAM) optimizes data transfer speeds by setting a minimum write size and using a temporary buffer in SRAM to update and copy parity data, ensuring efficient data transfer and storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parity data is generated and stored in RAM for each write command, then data protection reliability is improved, but RAM space consumption increases and cost increases

Engineering Contradiction:
Improvedata protectionVSAvoidRAM space
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The invention segments the storage system into zones, with each zone having its own dedicated parity die. This segmentation allows parity data to be distributed across multiple zones rather than concentrated in a single RAM area, effectively dividing the RAM space requirement into smaller manageable portions allocated to each zone.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from storing all parity data in a single RAM dimension to utilizing the zonal structure of the storage device. Parity data is now stored in association with specific zones and their corresponding dies, adding a spatial dimension (zone-based distribution) to the parity storage architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If data transfer speed to NAND is increased, then write performance is improved, but bottlenecks occur when simultaneously generating parity data for numerous small commands

Engineering Contradiction:
Improvedata transfer speedVSAvoidwrite throughput
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The invention implements preliminary action by pre-allocating parity storage space in RAM for each zone before write operations begin. This allows the system to prepare the necessary buffer space in advance, enabling faster data transfer to NAND without the overhead of dynamically allocating and managing parity storage during the write process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention ensures continuity of useful action by maintaining dedicated parity storage regions in RAM that are continuously available for each zone. This eliminates interruptions in the write process caused by parity generation and storage operations, allowing data transfer to NAND to proceed continuously without bottlenecks.

Inventive Principle:
Principle #20Continuity of useful action

3Quantity of substance

If more RAM is included in the storage device, then parity data storage capacity is improved, but overall device cost increases

Engineering Contradiction:
Improveparity data storage capacityVSAvoiddevice cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The invention makes the RAM serve multiple functions: it is used both for storing user data and for generating/storing parity data for each zone. This multi-functionality eliminates the need for separate dedicated RAM regions solely for parity storage, thereby reducing the total RAM capacity required and lowering device cost.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention changes the parameter of RAM allocation from a fixed large capacity to a dynamic zone-based allocation. Each zone receives only the amount of RAM space it needs for its parity data, optimizing the overall RAM utilization and reducing the total RAM capacity required compared to traditional approaches that allocate RAM uniformly or in large blocks.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11520660B2Storage devices hiding parity swapping behavior
Publication Date: 2022.12.06 SANDISK TECHNOLOGIES LLC
  • US11520660B2 patent drawing
  • US11520660B2 patent drawing
  • US11520660B2 patent drawing

AI summary

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. By restricting the host to have a minimum write size, the data transfer speed to RAM2, RAM1, and the storage unit can be optimized. A temporary buffer is utilized within the RAM1 to update parity data for the corresponding commands. The parity data is updated in the RAM1 and written to the RAM2 in the corresponding zone. The parity data may be copied from the RAM2 to the RAM1 to update the parity data in the temporary buffer when commands are received to write data to corresponding zones. As the parity data is updated, the corresponding command is simultaneously written to the corresponding zone.