Storage Device Controller Queues for Partial Read Output

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing storage devices face inefficiencies in data output and read operations due to varying times at which different memory devices provide read data, leading to potential delays in completing read operations without waiting for all data to be stored in a buffer memory.

Innovation Solution

A storage device with a controller that includes a descriptor queue and a buffer memory, allowing for efficient data storage and read operations by checking the status of data in the buffer memory and outputting data once it is ready, even if not all data is fully stored, using a circular linked list structure to manage descriptors and control units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the controller waits for all read data from multiple memory devices to be stored in the buffer memory before performing the next read operation, then data completeness is ensured, but read operation efficiency deteriorates due to waiting time

Engineering Contradiction:
Improvedata completenessVSAvoidread operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The controller performs the next read operation even when previous read data is not completely stored in the buffer memory. Instead of waiting for full completion, the controller initiates subsequent read commands based on descriptor queue status, accepting that some data may still be in transit. This partial completion approach eliminates waiting time and improves read operation throughput.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The controller checks the status of buffer memory and descriptor queue in advance to determine whether to initiate the next read operation. By performing preliminary status checks and preparing next commands ahead of time, the controller can seamlessly transition between read operations without waiting for complete data transfer, thereby improving efficiency while maintaining data integrity through status verification.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the controller checks the status of all read data in the buffer memory before outputting, then data readiness is confirmed, but output timing deteriorates due to additional check operations

Engineering Contradiction:
Improvedata readiness confirmationVSAvoidoutput timing
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The controller checks only the necessary portion of buffer memory status rather than all read data. When the descriptor queue indicates that sufficient data is available for the next output operation, the controller proceeds with partial status verification and immediately outputs data, avoiding unnecessary waiting and additional check operations that would delay output timing.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The controller continuously monitors buffer memory status and descriptor queue through feedback mechanisms. This real-time feedback allows the controller to dynamically determine when data is ready for output without performing exhaustive checks, enabling timely data output while maintaining reliability through ongoing status monitoring.

Inventive Principle:
Principle #23Feedback

3Device complexity

If the controller manages descriptors sequentially in a traditional queue, then simplicity is maintained, but read operation efficiency deteriorates due to inability to handle overlapping operations

Engineering Contradiction:
Improvedescriptor management simplicityVSAvoidread operation efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The descriptor queue is segmented into multiple descriptors that can be independently managed and processed. Each descriptor represents a separate read operation with its own status and data requirements. This segmentation allows the controller to handle multiple read operations in parallel or overlapping fashion, improving efficiency while maintaining manageable complexity through structured descriptor organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The descriptor queue management is made dynamic, allowing the controller to selectively process descriptors based on buffer status, data availability, and operation priorities. Rather than rigid sequential processing, the controller can jump between descriptors, reorder operations, and manage overlapping read commands flexibly, significantly improving read operation efficiency while maintaining systematic control.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12417034B2Storage device including controller and method of operating controller
Publication Date: 2025.09.16 SK HYNIX INC
  • US12417034B2 patent drawing
  • US12417034B2 patent drawing
  • US12417034B2 patent drawing

AI summary

The present technology relates to an electronic device. According to the present technology, a storage device includes a plurality of nonvolatile memory devices, a buffer memory configured to temporarily store data provided by the memory devices, and a controller including a descriptor queue storing a plurality of descriptors, wherein the controller controls the memory devices to perform a read operation corresponding to a first descriptor among the plurality of descriptors, performs a first status check operation of checking whether read data read through the read operation is stored in the buffer memory, and determines, based on a result of the first status check operation, read data to be output to an external device from among the read data read through the read operation.