Storage Controller Pin Mapping Using Command-Driven Data Patterns

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Solution Overview

Problem

The increase in size of storage devices due to the need for separate pins to determine connection methods between memory devices and storage controllers.

Innovation Solution

A storage controller and memory device system that uses a command to generate data patterns for determining connection structures between data pins without additional pins, allowing for various connection methods and reducing interference and signal integrity issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate pins are added to determine connection methods between memory devices and storage controllers, then connection method determination capability is improved, but device size increases

Engineering Contradiction:
Improveconnection method determination capabilityVSAvoiddevice size
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent merges the connection method determination function with existing data pins by utilizing data patterns embedded in commands and responses. Instead of adding separate pins, the connection structure information is encoded within the data transmitted during normal operation, allowing multiple functions to share the same physical infrastructure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The data pins are given multi-functionality by enabling them to serve both their original data transmission purpose and the additional function of conveying connection structure information. The command and response data patterns carry dual purposes: normal data operations and connection method identification, eliminating the need for dedicated pins.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If data patterns are transmitted through existing data lines to determine connection structures, then device size is reduced, but signal integrity may be affected by interference

Engineering Contradiction:
Improvedevice sizeVSAvoidsignal interference
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent performs connection structure determination during the initialization phase before normal data operations begin. By completing the connection identification using data patterns in advance, the system establishes proper communication parameters and connection mappings before actual data transmission, preventing interference issues during operational phases.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback mechanisms where the storage controller sends commands with specific data patterns and the memory device responds with corresponding patterns. By comparing the transmitted and received patterns, the controller can verify connection integrity and detect any interference, allowing for error correction and retransmission if necessary.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250383979A1Storage controller, storage device including the same, and operating method thereof
Publication Date: 2025.12.18 SAMSUNG ELECTRONICS CO LTD
  • US20250383979A1 patent drawing
  • US20250383979A1 patent drawing
  • US20250383979A1 patent drawing

AI summary

A storage device comprising a storage controller including a plurality of first data pins and configured to send a command through a command/address (CA) line, the command including a first data pattern; and a memory device including a plurality of second data pins connected to the plurality of first data pins through a plurality of data lines, and configured to, in response to receiving the command from the storage controller, generate a second data pattern corresponding to the first data pattern based on the command, and send the second data pattern to the storage controller through the plurality of data lines, and the storage controller configured to receive a third data pattern in response to the memory device sending the second data pattern, and determine a connection structure between the plurality of first data pins and the plurality of second data pins based on the second and third data patterns.