Storage Controller Port Selection for Write Data Redundancy
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Solution Overview
Problem
Conventional storage systems face increased processor load and decreased IO performance when simulating DMA transfer functions without ASICs, leading to inefficiencies in data transmission between storage systems.
Innovation Solution
A storage system architecture that includes multiple interface units and controllers, where a processor unit selects an optimal port for transmitting write data to another storage system within the same interface unit, reducing the need for inter-controller data transfer and thereby minimizing processor load and maintaining IO performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a processor simulates DMA transfer function without mounting ASIC, then hardware cost is reduced, but processor load increases and IO performance decreases
Solution Approach 1:
The storage system is divided into multiple independent controllers, each with its own interface units and ports. By segmenting the system this way, data transmission can occur within the same controller without requiring processor intervention for inter-controller transfers, thus reducing processor load while maintaining cost-effective processor simulation of DMA functions.
Solution Approach 2:
The patent introduces an intermediary mechanism where data is transmitted through ports within the same controller rather than directly through processor-managed memory. This intermediary port-based transmission path reduces the burden on the processor simulating DMA functions, addressing the performance degradation issue while keeping hardware costs low.
2Reliability
If write data is transmitted between different controllers, then data redundancy is achieved, but processor load increases
Solution Approach 1:
The system is segmented into multiple controllers with distinct port structures. Each controller can independently transmit data through its own ports, enabling data redundancy to be achieved through controlled transmission paths that minimize processor involvement and thus reduce processor load while maintaining reliability.
3Productivity
If multiple interface units and controllers are used to optimize data transmission paths, then processor load is reduced, but device complexity increases
Solution Approach 1:
The storage system is divided into multiple independent controllers, each with dedicated interface units and ports. This segmentation creates a modular architecture where data transmission can be handled locally within controllers, reducing processor load while the modular nature keeps complexity manageable through standardization.
Solution Approach 2:
Each controller is designed with universal functionality to handle multiple tasks including data reception, transmission, and port management. This multi-functionality allows the system to achieve reduced processor load through intelligent data routing without proportionally increasing device complexity, as each controller unit serves multiple purposes.
Data Source
AI summary
A storage system is coupled to another storage system and a higher-level apparatus via a network, and copies write data received from the higher-level apparatus to the other storage system. This storage system is provided with interface units, each provided with a plurality of ports that can be coupled to the network; and a plurality of controllers coupled to a respective one of the interface units. Each controller has a processor unit. When each processor unit receives write data from the higher-level apparatus via a first port coupled to the interface unit that is coupled to the controller to which the processor unit belongs, the processor unit selects, from among the ports of the interface unit coupled to the controller to which the processor unit belongs, a second port for transmitting the write data to the other storage system, and transmits the write data to the other storage system.