Clustered Storage Controller Prioritization via Interrupt Differentiation

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Solution Overview

Problem

In clustered storage systems without dedicated LSIs, processors face challenges in directly accessing hardware resources, leading to reduced response performance due to the need for interrupt requests and prioritization, which increases overhead and can delay I/O processing.

Innovation Solution

The system differentiates between prioritized and non-prioritized request information, allowing the second processor to prioritize processing based on the request type, preventing delays in I/O processing by using a dual-controller configuration with a PCI-Express bus connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a dedicated LSI is used for direct hardware access, then response performance is improved, but device complexity and cost increase

Engineering Contradiction:
Improveresponse performanceVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent replaces expensive, complex dedicated LSI hardware with a software-based interrupt handling mechanism that runs on general-purpose processors. This allows the system to achieve the required functionality without investing in costly specialized hardware components, effectively substituting disposable software solutions for permanent hardware fixes.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent substitutes the mechanical/electrical direct access path (dedicated LSI) with a software-based communication path (interrupt requests through the OS). This replacement transforms a hardware-centric access mechanism into a software-managed process, reducing hardware complexity while maintaining system functionality.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If interrupt requests are used for prioritized processing, then processing priority is improved, but overhead increases and I/O processing may be delayed

Engineering Contradiction:
Improveprocessing priorityVSAvoidoverhead
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements a self-service mechanism where the interrupt handler automatically identifies and processes high-priority requests without requiring external intervention or complex scheduling decisions. The system serves itself by having the interrupt mechanism inherently recognize and handle time-critical operations, reducing the need for additional overhead management.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the parameter of request identification by including priority information directly within the request data structure itself. This allows the system to differentiate and prioritize processing based on embedded parameters rather than requiring separate signaling mechanisms, thereby reducing overhead while maintaining prioritization capability.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the processor handles both host I/O processing and controller access requests, then resource utilization is improved, but response performance to controller requests deteriorates

Engineering Contradiction:
Improveresource utilizationVSAvoidresponse performance
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent applies local quality by treating different types of requests differently within the same processor. High-priority controller access requests receive expedited handling through the interrupt mechanism, while normal host I/O requests continue through the standard processing path. This localized differentiation allows the processor to optimize response performance for critical operations without sacrificing overall resource utilization.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent prepares the system in advance by establishing the interrupt handling framework and priority identification mechanisms before requests arrive. This preliminary setup ensures that when controller access requests occur, the processor can immediately recognize and prioritize them without delay, maintaining high response performance while continuing to handle host I/O operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9535864B2Computer system and control method thereof
Publication Date: 2017.01.03 HITACHI VANTARA LTD
  • US9535864B2 patent drawing
  • US9535864B2 patent drawing
  • US9535864B2 patent drawing

AI summary

The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.