Storage Controller Read Commands for Multi-Plane Voltage Alignment
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Solution Overview
Problem
Existing memory devices with multiple planes require significant power and time to correct address signal levels during read operations due to varying read voltage levels across planes.
Innovation Solution
A memory system that generates either a first read command signal with individual address signals for each plane or a second read command signal with a collective address signal, determining the command based on the deviation in read levels to optimize power and time efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a read command is generated based on an address signal level for one plane with correction during read operation, then the memory device can handle multiple planes with different read voltage levels, but the power and time consumed to correct address signal levels increases
Solution Approach 1:
The patent segments the address signal generation by creating separate command paths: first read command signals with plane-specific address signal levels for planes requiring correction, and second read command signals with collective address signal levels for planes not requiring correction. This segmentation allows selective application of correction operations only where needed, reducing overall power consumption while maintaining compatibility with multiple plane types.
Solution Approach 2:
The patent implements dynamic command selection that adapts to the specific read requirements of different planes. The system dynamically determines whether to issue first read commands (with correction) or second read commands (without correction) based on the target plane's characteristics, optimizing power consumption in real-time while maintaining the ability to handle diverse plane configurations.
2Measurement precision
If address signal level correction is performed during read operation on each plane, then read accuracy is maintained across planes with different voltage levels, but the time required for read operations increases
Solution Approach 1:
The patent divides read operations into two segmented paths: operations requiring address signal level correction (first read commands) and operations not requiring correction (second read commands). By segmenting the read process, the system applies correction operations only when necessary for read accuracy, thereby maintaining measurement precision while minimizing the time penalty associated with correction operations.
Solution Approach 2:
The patent applies address signal level correction locally only to specific planes that require it, rather than uniformly to all planes. This localized approach ensures read accuracy is maintained for planes with different voltage levels while avoiding unnecessary correction operations on planes that do not require them, thus reducing overall read operation time.
3Device complexity
If collective address signal is applied to all planes, then command generation is simplified, but the ability to optimize power consumption for planes with different read levels is reduced
Solution Approach 1:
The patent implements a dynamic command generation system that selectively switches between two command types: first read commands with plane-specific address signal levels for power optimization, and second read commands with collective address signal levels for simplified operation. This dynamic approach allows the system to balance complexity and power consumption optimization based on the specific read requirements of different planes.
Data Source
AI summary
A memory system includes a storage controller for transmitting a read command to a memory device including a plurality of planes, the memory system including a command generation module configured to generate a first read command signal including an address signal set for each of the plurality of planes or a second read command signal including an address signal applied collectively to the plurality of planes, a command selection module configured to determine either the first read command signal or the second read command signal as the read command, and a memory controller configured to transmit the determined read command to the memory device.