Storage Controller Reset via Cache Execution
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Solution Overview
Problem
Existing storage controller recovery processes are disruptive and time-consuming due to the need for hardware resets, which involve reloading microprocessor code, running self-tests, and updating global structures, causing significant disruptions to host operations.
Innovation Solution
An error handling routine that loads and executes reset operations from cache during SDRAM self-refresh mode, allowing for a non-disruptive memory controller reset without requiring power-on self-tests or built-in self-tests, by quiescing processes, flushing caches, and initializing configuration and interface registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hardware reset is performed to recover from adapter errors, then the system can clear errors and resume operation, but the recovery process is time-consuming and disruptive to host operations
Solution Approach 1:
The patent applies preliminary action by pre-loading the reset routine into the cache memory before an error occurs. When an adapter error happens, the reset routine is already available in the cache, eliminating the need to reload it from slower memory during the error recovery process, thus reducing reset time while maintaining reliability
Solution Approach 2:
The patent uses the cache as an intermediary between the main memory and the reset routine execution. By storing the reset routine in the cache, the system creates a faster execution path that mediates between the need for comprehensive reset operations and the desire for quick recovery, reducing the time loss associated with hardware resets
2Reliability
If a hardware reset is performed to recover from adapter errors, then the system can reinitialize registers and clear errors, but microprocessor code must be reloaded and self-tests must be run, causing significant disruptions to host operations
Solution Approach 1:
The reset routine is pre-loaded into the cache before an error occurs, so when an error happens, the system can immediately execute the reset from the cache without interrupting host operations for code reloading. This preliminary preparation maintains productivity while ensuring reliable error recovery
Solution Approach 2:
The patent creates a copy of the reset routine in the cache memory separate from the main memory location. This copy allows the system to execute the reset operation independently without requiring host operations to pause for code reloading, thus maintaining productivity while achieving reliable error recovery
3Reliability
If a hardware reset is performed, then global structures can be updated and registers initialized, but the process requires extensive sequential operations that disrupt host operations
Solution Approach 1:
By pre-loading the reset routine into the cache, the system performs the initialization operations in a more streamlined manner that can overlap with host operations. The reset routine is already prepared and can be executed without requiring host operations to wait for sequential code loading, reducing the disruption level while maintaining proper system initialization
Data Source
AI summary
An error handling method is provided for processing adapter errors. Rather than executing a disruptive controller hardware reset, an error handling routine provides instructions for a reset operation to be loaded and executed from cache while the SDRAM is in self-refresh mode and therefore unusable.