Storage Controller Scramble Circuit for Channel Load Balancing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face performance fluctuations due to uneven allocation of write requests across channels, leading to reduced performance as data of specific patterns are often focused on specific channels, causing channel overload and reduced deserialization of nonvolatile memory devices.
Innovation Solution
A storage controller with a scramble circuit that performs XOR and hash operations on logical addresses to generate scrambled addresses, allocating write requests uniformly across multiple channels and flash translation layers, ensuring balanced resource utilization and maintaining data sequentiality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is distributed to specific channels using conventional interleaving, then data management is simplified, but channel overload occurs and performance decreases
Solution Approach 1:
The patent changes the addressing parameter by scrambling the logical address bits using XOR operations with channel, way, and plane identifiers. This transforms the address distribution pattern from conventional sequential allocation to a scrambled pattern that evenly distributes data across all channels, preventing channel overload while maintaining manageable data routing through the scrambling algorithm.
2Speed
If consecutive logical memory areas are allocated to specific channels, then deserialization of nonvolatile memory devices is maximized, but data of specific patterns focuses on specific channels causing performance reduction
Solution Approach 1:
The patent introduces asymmetry in the address allocation pattern by scrambling the channel, way, and plane identifiers using XOR operations. This breaks the symmetric sequential allocation pattern where consecutive logical addresses map to consecutive physical locations, creating an asymmetric distribution that prevents pattern-focused data from concentrating on specific channels while maintaining efficient memory access.
3Productivity
If data is evenly distributed across channels using address scrambling, then channel overload is prevented and performance increases, but system complexity increases due to scramble circuit requirements
Solution Approach 1:
The patent replaces complex mechanical or software-based address translation mechanisms with a simple electronic XOR scramble circuit. This circuit uses bitwise XOR operations with channel, way, and plane identifiers to scramble logical addresses, achieving even data distribution across channels through a lightweight hardware implementation that adds minimal complexity compared to conventional address translation methods.
Data Source
AI summary
A storage controller including: a host interface circuit receiving first, second, third and fourth requests corresponding to first, second, third and fourth logical addresses; a memory interface circuit communicating with first nonvolatile memories through a first channel and second nonvolatile memories through a second channel; a first flash translation layer configured to manage the first nonvolatile memories; and a second flash translation layer configured to manage the second nonvolatile memories, the first flash translation layer outputs commands corresponding to the first and fourth requests through the first channel, and the second flash translation layer outputs commands respectively corresponding to the second and third requests through the second channel, and a value of the first logical address is smaller than a value of the second logical address, and a value of the third logical address is smaller than a value of the fourth logical address.