Storage Controller Signal Skewing to Reduce Memory Crosstalk
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Solution Overview
Problem
Storage devices face challenges in reducing crosstalk between the storage controller and nonvolatile memory devices when exchanging data signals in parallel, which affects signal integrity and performance.
Innovation Solution
Incorporating a first delay circuit in the storage controller to desynchronize data signals by different skew offsets and transmitting skew information to the nonvolatile memory devices, which includes a second delay circuit to align the signals and cancel the skew offsets, thereby reducing crosstalk and enhancing signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data signals are transmitted in parallel between storage controller and nonvolatile memory device, then data transmission speed is improved, but crosstalk occurs between adjacent signal lines
Solution Approach 1:
The patent applies preliminary action by desynchronizing data signals before transmission. The storage controller intentionally introduces skew offsets to different data signals (DQ<0> to DQ<31>) before they are transmitted through parallel signal lines. This preliminary timing adjustment ensures that signals do not transition simultaneously, preventing crosstalk from occurring in the first place during high-speed parallel data transmission between the storage controller and nonvolatile memory device.
2Reliability
If data signals are desynchronized by skew offsets to reduce crosstalk, then signal integrity is improved, but signal timing alignment becomes complex
Solution Approach 1:
The patent implements feedback by transmitting skew information from the storage controller to the nonvolatile memory device. The storage controller sends metadata indicating the applied skew offsets, enabling the nonvolatile memory device to automatically compensate for the intentional desynchronization. This feedback mechanism maintains signal integrity by ensuring proper timing alignment at the receiving end while keeping the overall system manageable through automated compensation rather than manual timing adjustment.
3Speed
If high-frequency signals are transmitted to enhance signal characteristic output, then data transmission performance is improved, but crosstalk and signal interference increase
Solution Approach 1:
The patent applies preliminary action by proactively desynchronizing high-frequency data signals before transmission occurs. By introducing skew offsets to different data signals (DQ<0> to DQ<31>) before they are transmitted through parallel signal lines, the system prevents crosstalk and signal interference from occurring during high-speed data transmission between the storage controller and nonvolatile memory device.
Data Source
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AI summary
A storage device includes a semiconductor memory device and a storage controller. The semiconductor memory device receives write data based on a data strobe signal and data signals, and outputs read data based on the data strobe signal and the data signals. The storage controller transmits the data strobe signal and the data signals in parallel to the semiconductor memory device through signal lines. The storage controller includes a first delay circuit that delays the data signals such that some edges of windows of the data signals on the signal lines are desynchronized by first skew offsets which are different from one another.